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公开(公告)号：US20090280643A1
公开(公告)日：2009-11-12
申请号：US12115568
申请日：2008-05-06
申请人： Paul S. Andry , Edward C. Cooney, III , Peter J. Lindgren , Dorreen J. Ossenkop , Cornelia K. Tsang
发明人： Paul S. Andry , Edward C. Cooney, III , Peter J. Lindgren , Dorreen J. Ossenkop , Cornelia K. Tsang
IPC分类号： H01L23/482 , H01L21/768 , H01L21/44 , H01L23/48 , H01L29/40 , H01L23/52
CPC分类号： H01L23/485 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater. Next, a conductive metal is formed on the conductive metal nucleation layer. After performing the above processing steps, a backside planarization process is performed to convert the at least one aperture into at least one through via that is now optimally filled with a conductive metal.
摘要翻译： 提供了一种在具有例如W的导电金属的直通晶片通孔结构内最佳地填充通孔的方法。 本发明的方法包括提供一种结构，其包括具有至少一个通过该基底部分形成的孔的基底。 该结构的至少一个孔具有至少20:1或更大的纵横比。 接下来，在至少一个孔内的衬底的裸露的侧壁上形成诸如Ti / TiN的含难熔金属衬里。 然后在含难熔金属的衬垫上形成导电金属种子层。 在本发明中，所形成的导电金属晶种层富含硅，其晶粒尺寸为约5nm或更小。 接着，在导电性金属种子层上形成导电性金属成核层。 导电金属成核层也富含硅，其粒径约为20nm或更大。 接着，在导电性金属成核层上形成导电性金属。 在执行上述处理步骤之后，执行背面平面化处理以将至少一个孔转换成现在被最佳地填充有导电金属的至少一个通孔。
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公开(公告)号：US07741226B2
公开(公告)日：2010-06-22
申请号：US12115568
申请日：2008-05-06
申请人： Paul S. Andry , Edward C. Cooney, III , Peter J. Lindgren , Dorreen J. Ossenkop , Cornelia K. Tsang
发明人： Paul S. Andry , Edward C. Cooney, III , Peter J. Lindgren , Dorreen J. Ossenkop , Cornelia K. Tsang
IPC分类号： H01L21/311
CPC分类号： H01L23/485 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater. Next, a conductive metal is formed on the conductive metal nucleation layer. After performing the above processing steps, a backside planarization process is performed to convert the at least one aperture into at least one through via that is now optimally filled with a conductive metal.
摘要翻译： 提供了一种在具有例如W的导电金属的直通晶片通孔结构内最佳地填充通孔的方法。 本发明的方法包括提供一种结构，其包括具有至少一个通过该基底部分形成的孔的基底。 该结构的至少一个孔具有至少20:1或更大的纵横比。 接下来，在至少一个孔内的衬底的裸露的侧壁上形成诸如Ti / TiN的含难熔金属衬里。 然后在含难熔金属的衬垫上形成导电金属种子层。 在本发明中，所形成的导电金属晶种层富含硅，其晶粒尺寸为约5nm或更小。 接着，在导电性金属种子层上形成导电性金属成核层。 导电金属成核层也富含硅，其粒径约为20nm或更大。 接着，在导电性金属成核层上形成导电性金属。 在执行上述处理步骤之后，执行背面平面化处理以将至少一个孔转换成现在被最佳地填充有导电金属的至少一个通孔。
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公开(公告)号：US20120115303A1
公开(公告)日：2012-05-10
申请号：US13354371
申请日：2012-01-20
IPC分类号： H01L21/4763 , H01L21/02
CPC分类号： H01L21/76802 , H01L21/76807 , H01L23/5223 , H01L28/40 , H01L2221/1021 , H01L2221/1063
摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.
摘要翻译： 在集成电路中形成导线的方法。 所述方法包括在基板上的第一电介质层中形成导线; 在所述导线和所述第一介电层上形成介电阻挡层; 在阻挡层上形成第二电介质层; 在所述第二介电层上形成一个或多个图案化的光致抗蚀剂层; 执行反应离子蚀刻以蚀刻通过第二介电层而不穿过阻挡层的沟槽; 执行第二反应离子蚀刻以将沟槽延伸穿过阻挡层; 并且在执行第二反应离子蚀刻之后，去除一个或多个图案化的光致抗蚀剂层，使用还原等离子体或非氧化等离子体去除最后形成的图案化光致抗蚀剂层。 所述方法包括通过与金属 - 绝缘体 - 金属电容器类似的方法形成导线。
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公开(公告)号：US07968975B2
公开(公告)日：2011-06-28
申请号：US12188234
申请日：2008-08-08
CPC分类号： H01L23/522 , H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.
摘要翻译： 通过半导体衬底和接触通过级介电层形成贯穿衬底通孔（TSV）的阵列。 直接在接触通路层电介质层上形成嵌入其中的金属线电介质层和线路级金属布线结构。 线级金属布线结构包括填充有金属线级介电层的隔离部分的奶酪孔。 在一个实施例中，整个烘干孔位于TSV阵列的区域的外部，以使TSV和线路级金属布线结构之间的接触面积达到最大。 在另一个实施例中，形成了覆盖TSV阵列中的整个接缝的一组干酪孔，以防止在电镀过程中在TSV的接缝中捕获任何电镀溶液，以防止接缝处的TSV的腐蚀。
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5.发明申请Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors 有权具有VIAS和高密度电容器的结构，设计结构和制造方法公开(公告)号：US20100038750A1
公开(公告)日：2010-02-18
申请号：US12191385
申请日：2008-08-14
CPC分类号： H01L29/66181 , H01L29/945
摘要： A semiconductor structure and design structure includes at least a first trench and a second trench having different depths arranged in a substrate, a capacitor arranged in the first trench, and a via arranged in the second trench.
摘要翻译： 半导体结构和设计结构至少包括布置在衬底中的具有不同深度的第一沟槽和第二沟槽，布置在第一沟槽中的电容器和布置在第二沟槽中的通孔。
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6.发明申请IC CHIP AND DESIGN STRUCTURE WITH THROUGH WAFER VIAS DISHING CORRECTION 有权通过WAVER VIAS DISHING CORRECTION进行IC芯片和设计结构公开(公告)号：US20100025857A1
公开(公告)日：2010-02-04
申请号：US12181467
申请日：2008-07-29
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684
摘要： An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.
摘要翻译： 具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。
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公开(公告)号：US08674423B2
公开(公告)日：2014-03-18
申请号：US13302168
申请日：2011-11-22
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译： 制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。 半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。 第一和第二沟槽在衬底中具有不同的深度。
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8.发明授权Distributed and interactive database architecture for parallel and asynchronous data processing of complex data and for real-time query processing 有权分布式和交互式数据库架构，用于并行和异步数据处理复杂数据和实时查询处理公开(公告)号：US08510329B2
公开(公告)日：2013-08-13
申请号：US11137618
申请日：2005-05-25
IPC分类号： G06F17/30
CPC分类号： G06Q10/10 , G06F17/30592
摘要： The various embodiments of the invention provide a data processing system and method, for applications such as marketing campaign management, speech recognition and signal processing. An exemplary system embodiment includes a first data repository adapted to store a plurality of entity and attribute data; a second data repository adapted to store a plurality of entity linkage data; a metadata data repository adapted to store a plurality of metadata modules, with a first metadata module having a plurality of selectable parameters, received through a control interface, and having a plurality of metadata linkages to a first subset of metadata modules; and a multidimensional data structure. The control interface may modify the plurality of selectable parameters in response to received control information. A plurality of processing nodes are adapted to use the plurality of selectable parameters to assemble a first plurality of data from the first and second data repositories and from input data, to reduce the first plurality of data to form a second plurality of data, and to aggregate and dimension the second plurality of data for storage in the multidimensional data structure.
摘要翻译： 本发明的各种实施例为营销活动管理，语音识别和信号处理等应用提供数据处理系统和方法。 示例性系统实施例包括适于存储多个实体和属性数据的第一数据仓库; 适于存储多个实体连接数据的第二数据仓库; 元数据数据仓库，其适于存储多个元数据模块，具有通过控制接口接收的具有多个可选择参数的第一元数据模块，以及具有多个元数据链接到元数据模块的第一子集; 和多维数据结构。 控制接口可以响应于接收到的控制信息来修改多个可选参数。 多个处理节点适于使用多个可选参数来组合来自第一和第二数据存储库和输入数据的第一多个数据，以减少第一多个数据以形成第二多个数据，并且 聚合和维度第二多个数据以存储在多维数据结构中。
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9.发明授权Structure and design structure for high-Q value inductor and method of manufacturing the same 有权高Q值电感器的结构和设计结构及其制造方法公开(公告)号：US08232173B2
公开(公告)日：2012-07-31
申请号：US12917029
申请日：2010-11-01
申请人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
发明人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L28/10 , H01L21/76898 , H01L23/5227 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.
摘要翻译： 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能性表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口的多个垂直开口中的第二个 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。
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公开(公告)号：US08119522B1
公开(公告)日：2012-02-21
申请号：US12941184
申请日：2010-11-08
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76807 , H01L23/5223 , H01L28/40 , H01L2221/1021 , H01L2221/1063
摘要： Method of forming wires in integrated circuits. The methods include forming a wire in a first dielectric layer on a substrate; forming a dielectric barrier layer over the wire and the first dielectric layer; forming a second dielectric layer over the barrier layer; forming one or more patterned photoresist layers over the second dielectric layer; performing a reactive ion etch to etch a trench through the second dielectric layer and not through the barrier layer; performing a second reactive ion etch to extend the trench through the barrier layer; and after performing the second reaction ion etch, removing the one or more patterned photoresist layers, a last formed patterned photoresist layer removed using a reducing plasma or a non-oxidizing plasma. The methods include forming wires by similar methods to a metal-insulator-metal capacitor.
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