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    Bimodal serial to parallel converter with bitslip controller
    2.
    发明授权
    Bimodal serial to parallel converter with bitslip controller 有权
    双模串行到并行转换器与位滑控制器

    公开(公告)号：US06985096B1

    公开(公告)日：2006-01-10

    申请号：US10919900

    申请日：2004-08-17

    申请人： Paul T. Sasaki ,  Jason R. Bergendahl ,  Atul Ghia ,  Jian Tan

    发明人： Paul T. Sasaki ,  Jason R. Bergendahl ,  Atul Ghia ,  Jian Tan

    IPC分类号： H03M9/00

    CPC分类号： H03M9/00 ,  H03K5/135

    摘要： Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate (“SDR”) data, and the latter configuration is for Double Data Rate (“DDR”) data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.

    摘要翻译： 提供了一种双模串并转换器的方法和装置。 响应于时钟信号（诸如同步接口的转发时钟信号）对寄存器的第一级进行时钟控制。 寄存器的第一级可以在单个串行移位链或两个串行移位链中进行配置。 前一种配置用于单数据速率（“SDR”）数据，后一种配置用于双倍数据速率（“DDR”）数据。 位位控制器被配置为向选择电路提供控制选择信号。 对于DDR操作，控制信号用于选择来自两个串行移位链的输出的相应部分以提供给第二级寄存器。 对于DDR操作，响应于时钟信号的分频版本和周期性地停止的时钟信号的另一个分频模式，寄存器的第二级可选地进行时钟控制。

    Reversible input/output delay line for bidirectional input/output blocks
    3.
    发明授权
    Reversible input/output delay line for bidirectional input/output blocks 有权
    用于双向输入/输出块的可逆输入/输出延迟线

    公开(公告)号：US07589557B1

    公开(公告)日：2009-09-15

    申请号：US11405901

    申请日：2006-04-18

    申请人： Jason R. Bergendahl ,  Qi Zhang ,  Jian Tan ,  Matthew H. Klein

    发明人： Jason R. Bergendahl ,  Qi Zhang ,  Jian Tan ,  Matthew H. Klein

    IPC分类号： H03K19/173

    CPC分类号： H03K5/159 ,  H03K19/017581 ,  H03K19/01759

    摘要： An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.

    摘要翻译： 输入/输出（I / O）结构包括在用户设计中可用于输入路径，输出路径或输入和输出路径的延迟元件。 在第一模式中，延迟元件包括在输入路径中。 在第二模式中，延迟元件包括在输出路径中。 在第三模式中，I / O结构包括输出信号路径和输入信号路径中的延迟，例如通过利用输出三态信号来控制延迟线的方向。 当输出缓冲区正在驱动时，延迟被插入到输出路径中。 当输出缓冲器被三态时，延迟被插入到输入路径中。 因此，单个延迟元件由使用相同I / O焊盘的输入和输出信号动态共享。 在可选的第四模式中，延迟元件被输入和输出信号旁路。

    Digitally controlled impedance for I/O of an integrated circuit device
    4.
    发明授权
    Digitally controlled impedance for I/O of an integrated circuit device 有权
    用于集成电路器件的I / O的数字控制阻抗

    公开(公告)号：US06489837B2

    公开(公告)日：2002-12-03

    申请号：US10007167

    申请日：2001-11-30

    申请人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

    发明人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

    IPC分类号： G05F110

    CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H04L25/0278

    摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

    摘要翻译： 提供一种用于控制集成电路芯片上的电路的阻抗的系统。 选择至少一个电路作为p沟道参考电路工作，并且选择至少一个电路作为n沟道参考电路进行工作。 选择其他电路用作电路和/或线路终端电路。 数字控制阻抗（DCI）电路控制p沟道参考电路以确定用于电路中的p沟道晶体管的期望配置。 DCI电路进一步控制n沟道参考电路以确定在电路中使用的n沟道晶体管的期望配置。 DCI电路考虑了p沟道参考电路中p沟道晶体管的电阻，n沟道参考电路中n沟道晶体管的电阻以及温度，电压和工艺变化等因素。 DCI电路将识别n沟道和p沟道晶体管的期望配置的信息中继到电路。 然后响应于该信息配置电路。

    Digitally controlled impedance for I/O of an integrated circuit device
    5.
    发明授权
    Digitally controlled impedance for I/O of an integrated circuit device 有权

    公开(公告)号：US06445245B1

    公开(公告)日：2002-09-03

    申请号：US09684539

    申请日：2000-10-06

    申请人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

    发明人： David P. Schultz ,  Suresh M. Menon ,  Eunice Y. D. Hao ,  Jason R. Bergendahl ,  Jian Tan

    IPC分类号： G05F110

    CPC分类号： H03K19/00384 ,  H03K19/0005 ,  H04L25/0278

    摘要： A system for controlling the impedances of circuits on an integrated circuit chip is provided. At least one circuit is selected to operate as a p-channel reference circuit, and at least one circuit is selected to operate as an n-channel reference circuit. Other circuits are selected to operate as circuits and/or line termination circuits. A digitally controlled impedance (DCI) circuit controls the p-channel reference circuit to determine a desired configuration of p-channel transistors for use in the circuits. The DCI circuit further controls the n-channel reference circuit to determine a desired configuration of n-channel transistors for use in the circuits. The DCI circuit takes into account such factors as resistances of p-channel transistors in the p-channel reference circuit, resistances of n-channel transistors in the n-channel reference circuit, as well as temperature, voltage and process variations. The DCI circuit relays information identifying the desired configurations of the n-channel and p-channel transistors to the circuits. The circuits are then configured in response to this information.

    Power distribution network
    6.
    发明授权
    Power distribution network 有权
    配电网络

    公开(公告)号：US08410579B2

    公开(公告)日：2013-04-02

    申请号：US12962613

    申请日：2010-12-07

    申请人： Atul V. Ghia ,  Christopher P. Wyland ,  Ketan Sodha ,  Paul T. Sasaki ,  Jian Tan ,  Paul Y. Wu ,  Romi Mayder

    发明人： Atul V. Ghia ,  Christopher P. Wyland ,  Ketan Sodha ,  Paul T. Sasaki ,  Jian Tan ,  Paul Y. Wu ,  Romi Mayder

    IPC分类号： H01L23/64 ,  H01L21/02

    CPC分类号： H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

    摘要翻译： 在一个实施例中，呈现集成电路（IC）。 IC包括形成在IC中的第一组和第二组配电线。 IC包括形成在IC的一个或多个层中的第一和第二电容器。 第一多个通孔将第一和第二电容器的第一输入耦合到第一组配电线，以及第二多个通孔将第一和第二电容器的第二输入端耦合到第二组配电线路。 第一电容器和第一多个通孔以及耦合到其上的第二多个通孔具有大于第二电容器和第一多个通孔和第二多个通孔耦合的等效串联电阻的等效串联电阻。

    POWER DISTRIBUTION NETWORK
    7.
    发明申请
    POWER DISTRIBUTION NETWORK 有权
    功率分配网络

    公开(公告)号：US20120139083A1

    公开(公告)日：2012-06-07

    申请号：US12962613

    申请日：2010-12-07

    申请人： Atul V. Ghia ,  Christopher P. Wyland ,  Ketan Sodha ,  Paul T. Sasaki ,  Jian Tan ,  Paul Y. Wu ,  Romi Mayder

    发明人： Atul V. Ghia ,  Christopher P. Wyland ,  Ketan Sodha ,  Paul T. Sasaki ,  Jian Tan ,  Paul Y. Wu ,  Romi Mayder

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

    摘要翻译： 在一个实施例中，呈现集成电路（IC）。 IC包括形成在IC中的第一组和第二组配电线。 IC包括形成在IC的一个或多个层中的第一和第二电容器。 第一多个通孔将第一和第二电容器的第一输入耦合到第一组配电线，以及第二多个通孔将第一和第二电容器的第二输入端耦合到第二组配电线路。 第一电容器和第一多个通孔以及耦合到其上的第二多个通孔具有大于第二电容器和第一多个通孔和第二多个通孔耦合的等效串联电阻的等效串联电阻。