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23 条记录 (耗时 0.021 秒)

    Field effect transistor
    1.
    发明授权
    Field effect transistor 失效
    场效应晶体管

    公开(公告)号：US06707120B1

    公开(公告)日：2004-03-16

    申请号：US09097991

    申请日：1998-06-16

    申请人： Payman Aminzadeh ,  Reza Arghavani ,  Peter Moon

    发明人： Payman Aminzadeh ,  Reza Arghavani ,  Peter Moon

    IPC分类号： H01L2976

    CPC分类号： H01L29/6659 ,  H01L21/3144 ,  H01L29/4983 ,  H01L29/6656

    摘要： A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.

    摘要翻译： 公开了一种制造具有增加的抗热载体损伤的场效应晶体管的方法。 在栅电极上生长氧化物。 该氧化物通过氮化和退火得到加强。 在轻掺杂漏极注入之后，沉积第二侧面氧化物和共形氮化物层。 然后，各向异性蚀刻共形氮化物以形成用于掩蔽高剂量漏极植入物的间隔物。 已经发现用该方法制造的NMOS过渡器比传统的轻掺杂漏极工艺对热载体损伤的敏感性低40％。 此外，该方法已证明比侧氧化物被氮化并再次氧化的方法更可制造。

    Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
    2.
    发明授权
    Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode 失效
    通过对栅电极的侧壁氧化物进行氮化和退火来制造具有增加的热载流子电阻的晶体管的方法

    公开(公告)号：US5827769A

    公开(公告)日：1998-10-27

    申请号：US754219

    申请日：1996-11-20

    申请人： Payman Aminzadeh ,  Reza Arghavani ,  Peter Moon

    发明人： Payman Aminzadeh ,  Reza Arghavani ,  Peter Moon

    IPC分类号： H01L21/314 ,  H01L21/336 ,  H01L29/49 ,  H01L21/31

    CPC分类号： H01L29/6659 ,  H01L21/3144 ,  H01L29/4983 ,  H01L29/6656

    摘要： A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.

    摘要翻译： 公开了一种制造具有增加的抗热载体损伤的场效应晶体管的方法。 在栅电极上生长氧化物。 该氧化物通过氮化和退火得到加强。 在轻掺杂漏极注入之后，沉积第二侧面氧化物和共形氮化物层。 然后，各向异性蚀刻共形氮化物以形成用于掩蔽高剂量漏极植入物的间隔物。 已经发现用该方法制造的NMOS过渡器比传统的轻掺杂漏极工艺对热载体损伤的敏感性低40％。 此外，该方法已证明比侧氧化物被氮化并再次氧化的方法更可制造。

    Method of forming an air gap intermetal layer dielectric (ILD) by utilizing a dielectric material to bridge underlying metal lines
    3.
    发明授权
    Method of forming an air gap intermetal layer dielectric (ILD) by utilizing a dielectric material to bridge underlying metal lines 有权
    通过利用介电材料桥接下面的金属线形成气隙金属间电介质（ILD）的方法

    公开(公告)号：US06908829B2

    公开(公告)日：2005-06-21

    申请号：US10094875

    申请日：2002-03-11

    申请人： Makarem A. Hussein ,  Peter Moon ,  Jim Powers ,  Kevin P. O'Brien

    发明人： Makarem A. Hussein ,  Peter Moon ,  Jim Powers ,  Kevin P. O'Brien

    IPC分类号： H01L23/522 ,  H01L21/76 ,  H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an air gap intermetal layer dielectric (ILD) to reduce capacitive coupling between electrical conductors in proximity. The method entails forming first and second electrical conductors over a substrate, wherein the electrical conductors are laterally spaced apart by a gap. Then, forming a gap bridging dielectric layer that extends over the first electrical conductor, the gap, and the second electrical conductor. In order to form a bridge from one electrical conductor to the other electrical conductor, the gap bridging dielectric materials should have poor gap filling characteristics. This can be attained by selecting and/or modifying a dielectric material to have a sufficiently high molecular weight and/or surface tension characteristic such that the material does not substantially sink into the gap. An example of such a material is a spin-on-polymer with a surfactant and/or other additives.

    摘要翻译： 一种形成气隙金属间电介质（ILD）的方法，以减少接近的电导体之间的电容耦合。 该方法需要在衬底上形成第一和第二电导体，其中电导体横向间隔开间隙。 然后，形成在第一电导体，间隙和第二电导体上延伸的间隙桥接电介质层。 为了形成从一个电导体到另一个电导体的桥接，桥接介电材料的间隙应具有差的间隙填充特性。 这可以通过选择和/或改性电介质材料来实现，以具有足够高的分子量和/或表面张力特性，使得材料基本上不会沉入间隙。 这种材料的一个实例是具有表面活性剂和/或其它添加剂的旋涂聚合物。

    Method for an improved air gap interconnect structure
    5.
    发明申请
    Method for an improved air gap interconnect structure 有权
    改进气隙互连结构的方法

    公开(公告)号：US20080044999A1

    公开(公告)日：2008-02-21

    申请号：US11893870

    申请日：2007-08-15

    申请人： Valery Dubin ,  Peter Moon

    发明人： Valery Dubin ,  Peter Moon

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.

    摘要翻译： 在一个实施例中，一种装置包括具有在层间电介质（ILD）中形成的至少一个互连的第一层，在第一层上形成的具有第二至少一个互连的第二层，在第二层上形成的第三层， 第三层限定第二至少一个互连和第三层之间的至少一个空气间隙，以及至少一个分流器，其选择性地覆盖第一和第二至少一个互连。 在另一个实施例中，一种方法包括形成包括ILD和第一至少一个互连的第一层，在第一层上形成第二层，第二层具有第二至少一个互连，在第一层上沉积至少一个分流 以及第二至少一个互连，在所述第二层上形成第三层，以及蒸发所述第二层的一部分以在所述第二至少一个互连和所述第三层之间产生至少一个空气间隙。

    Damascene interconnect structures
    7.
    发明申请
    Damascene interconnect structures 审中-公开
    大马士革互连结构

    公开(公告)号：US20050146048A1

    公开(公告)日：2005-07-07

    申请号：US10748359

    申请日：2003-12-30

    申请人： Valery Dubin ,  Peter Moon ,  Kevin O'Brien

    发明人： Valery Dubin ,  Peter Moon ,  Kevin O'Brien

    IPC分类号： H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/76843 ,  H01L21/76862 ,  H01L21/76865

    摘要： A method for making a semiconductor device is provided including providing a substrate, and forming a dielectric layer over the substrate. The method also includes defining a damascene interconnect structure in the dielectric layer and forming a barrier layer over the dielectric layer and within the damascene interconnect structure where the barrier layer is tapered within the damascene interconnect structure.

    摘要翻译： 提供一种制造半导体器件的方法，包括提供衬底，并在衬底上形成电介质层。 该方法还包括在电介质层中限定镶嵌互连结构，并在电介质层之上和镶嵌互连结构内形成阻挡层，其中阻挡层在镶嵌互连结构内呈锥形。

    Apparatus for an improved air gap interconnect structure
    9.
    发明申请
    Apparatus for an improved air gap interconnect structure 有权
    用于改进气隙互连结构的装置

    公开(公告)号：US20070284744A1

    公开(公告)日：2007-12-13

    申请号：US11893869

    申请日：2007-08-15

    申请人： Valery Dubin ,  Peter Moon

    发明人： Valery Dubin ,  Peter Moon

    IPC分类号： H01L23/528

    CPC分类号： H01L21/76843 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.

    摘要翻译： 在一个实施例中，一种装置包括具有在层间电介质（ILD）中形成的至少一个互连的第一层，在第一层上形成的具有第二至少一个互连的第二层，在第二层上形成的第三层， 第三层限定第二至少一个互连和第三层之间的至少一个空气间隙，以及至少一个分流器，其选择性地覆盖第一和第二至少一个互连。 在另一个实施例中，一种方法包括形成包括ILD和第一至少一个互连的第一层，在第一层上形成第二层，第二层具有第二至少一个互连，在第一层上沉积至少一个分流 以及第二至少一个互连，在所述第二层上形成第三层，以及蒸发所述第二层的一部分以在所述第二至少一个互连和所述第三层之间产生至少一个空气间隙。