公开(公告)号：US08013377B2

公开(公告)日：2011-09-06

申请号：US12269612

申请日：2008-11-12

申请人： Peter Baars ,  Stefan Tegen ,  Klaus Muemmler

发明人： Peter Baars ,  Stefan Tegen ,  Klaus Muemmler

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/90 ,  H01L27/10852

摘要： Embodiments of the invention relate to an integrated circuit comprising a carrier, having a capacitor with a first electrode and a second electrode. The first electrode has a dielectric layer A layer sequence is arranged on the carrier, the capacitor being introduced in said layer sequence, wherein the layer sequence has a first supporting layer and a second supporting layer arranged at a distance above the first supporting layer, wherein the first and the second supporting layer adjoin the first electrode of the capacitor. Methods of manufacturing the integrated circuit are also provided.

摘要翻译： 本发明的实施例涉及一种包括载体的集成电路，其具有具有第一电极和第二电极的电容器。 第一电极具有电介质层A层序列布置在载体上，电容器以所述层序列引入，其中层序列具有布置在第一支撑层上方一段距离处的第一支撑层和第二支撑层，其中 第一和第二支撑层邻接电容器的第一电极。 还提供了制造集成电路的方法。

公开(公告)号：US20100032635A1

公开(公告)日：2010-02-11

申请号：US12188401

申请日：2008-08-08

申请人： Ulrike Gruening-von Schwerin ,  Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Thomas Happ

发明人： Ulrike Gruening-von Schwerin ,  Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Thomas Happ

IPC分类号： H01L47/00 ,  H01L29/66 ,  H01L21/00

CPC分类号： H01L27/24 ,  Y10S257/91

摘要： An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.

摘要翻译： 描述了包括存储器单元阵列和相应的制造方法的集成电路。 每个存储单元包括电阻切换存储器元件和耦合到选择线沟槽中的选择线的垂直选择二极管，用于从多个存储器单元中选择一个单元。 选择线在选择线沟槽的一个垂直侧壁处耦合到垂直选择二极管。

公开(公告)号：US07659602B2

公开(公告)日：2010-02-09

申请号：US12131728

申请日：2008-06-02

申请人： Stefan Tegen ,  Klaus Muemmler ,  Peter Baars ,  Odo Wunnicke

发明人： Stefan Tegen ,  Klaus Muemmler ,  Peter Baars ,  Odo Wunnicke

IPC分类号： H01L49/00

CPC分类号： H01L28/90 ,  H01L28/86

摘要： A structure and method of forming a capacitor is described. In one embodiment, the capacitor includes a cylindrical first electrode having an inner portion bounded by a bottom surface and an inner sidewall surface, the first electrode further having an outer sidewall, the first electrode being formed from a conductive material. An insulating fill material is disposed within the inner portion of the first electrode. A capacitor dielectric is disposed adjacent at least a portion of the outer sidewall of the first electrode. A second electrode is disposed adjacent the outer sidewall of the first electrode and separated therefrom by the capacitor dielectric. The second electrode is not formed within the inner portion of the first electrode.

摘要翻译： 描述形成电容器的结构和方法。 在一个实施例中，电容器包括圆柱形第一电极，其具有由底表面和内侧壁表面限定的内部部分，第一电极还具有外侧壁，第一电极由导电材料形成。 绝缘填充材料设置在第一电极的内部部分内。 电容器电介质设置在第一电极的外侧壁的至少一部分附近。 第二电极邻近第一电极的外侧壁设置，并由电容器电介质分离。 第二电极不形成在第一电极的内部。

公开(公告)号：US20090008694A1

公开(公告)日：2009-01-08

申请号：US11825228

申请日：2007-07-05

申请人： Klaus Muemmler ,  Peter Baars ,  Stefan Tegen

发明人： Klaus Muemmler ,  Peter Baars ,  Stefan Tegen

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7827

摘要： The present invention provides an integrated circuit including a field effect transistor formed in an active area segment of a semiconductor substrate, the transistor comprising: a first and a second source/drain contact region; and a channel region arranged in a groove formed in the active area segment and extending to a groove depth larger than a lower first contact depth, wherein the second source/drain contact region is arranged at a vertical extension above the extension of the first source/drain contact region and a corresponding manufacturing method.

摘要翻译： 本发明提供一种集成电路，其包括形成在半导体衬底的有源区段中的场效应晶体管，该晶体管包括：第一和第二源极/漏极接触区域; 以及沟槽区域，布置在形成在有源区段中的沟槽中并且延伸到大于下第一接触深度的沟槽深度，其中第二源极/漏极接触区域布置成在第一源极/漏极接触区域的延伸部之上的垂直延伸部处， 漏极接触区域和相应的制造方法。

公开(公告)号：US20070037334A1

公开(公告)日：2007-02-15

申请号：US11203927

申请日：2005-08-15

申请人： Klaus Muemmler ,  Stefan Tegen ,  Peter Baars ,  Joern Regul

发明人： Klaus Muemmler ,  Stefan Tegen ,  Peter Baars ,  Joern Regul

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L28/90 ,  H01L27/105 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897

摘要： The invention relates to a method of forming a memory device comprising a memory cell array and a peripheral portion. When forming the capacitors in the memory cell array, a sacrificial layer is deposited which is usually made of silicon dioxide and which is used for defining the storage electrode above the substrate surface. The sacrificial layer is removed selectively from the array portion while being maintained in the peripheral portion. This is achieved by providing an array separation trench which acts as a lateral etch stop.

摘要翻译： 本发明涉及一种形成包括存储单元阵列和周边部分的存储器件的方法。 当在存储单元阵列中形成电容器时，沉积牺牲层，该牺牲层通常由二氧化硅制成，并且用于在衬底表面上限定存储电极。 牺牲层在保持在周边部分的同时从阵列部分选择性地移除。 这通过提供用作横向蚀刻停止的阵列分离沟槽来实现。

公开(公告)号：US08125006B2

公开(公告)日：2012-02-28

申请号：US12188401

申请日：2008-08-08

申请人： Ulrike Gruening-von Schwerin ,  Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Thomas Happ

发明人： Ulrike Gruening-von Schwerin ,  Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Thomas Happ

IPC分类号： H01L29/768

CPC分类号： H01L27/24 ,  Y10S257/91

摘要： An integrated circuit comprising an array of memory cells and a corresponding production method are described. Each memory cell comprises a resistively switching memory element and a vertical selection diode coupled to a selection line in a selection line trench for selecting one cell from the plurality of memory cells. A selection line is coupled to the vertical selection diode at one vertical sidewall of the selection line trench.

摘要翻译： 描述了包括存储器单元阵列和相应的制造方法的集成电路。 每个存储单元包括电阻切换存储器元件和耦合到选择线沟槽中的选择线的垂直选择二极管，用于从多个存储器单元中选择一个单元。 选择线在选择线沟槽的一个垂直侧壁处耦合到垂直选择二极管。

公开(公告)号：US07952138B2

公开(公告)日：2011-05-31

申请号：US11825228

申请日：2007-07-05

申请人： Klaus Muemmler ,  Peter Baars ,  Stefan Tegen

发明人： Klaus Muemmler ,  Peter Baars ,  Stefan Tegen

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66666 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/7827

摘要： An integrated circuit includes a field effect transistor formed in an active area segment of a semiconductor substrate. The transistor comprises: a first source/drain contact region including a first vertical extension and a second source/drain contact region including a second vertical extension and a channel region formed around a recessed channel transistor groove, the groove being formed in the active area segment and extending to a groove depth larger than a lower first contact region depth, wherein the second vertical extension of the second source/drain contact region is arranged above the first extension of the first source/drain contact region, and wherein the recessed channel transistor groove is filled with a conductive gate material at a groove depth lower than the first contact region depth.

摘要翻译： 集成电路包括形成在半导体衬底的有源区段中的场效应晶体管。 晶体管包括：包括第一垂直延伸的第一源极/漏极接触区域和包括第二垂直延伸部的第二源极/漏极接触区域和形成在凹陷沟道晶体管沟槽周围的沟道区域，所述沟槽形成在有源区域段中 并且延伸到大于下部第一接触区域深度的凹槽深度，其中所述第二源极/漏极接触区域的所述第二垂直延伸部布置在所述第一源极/漏极接触区域的所述第一延伸部之上，并且其中所述凹入沟道晶体管沟槽 在低于第一接触区域深度的槽深处填充有导电栅极材料。

公开(公告)号：US07851356B2

公开(公告)日：2010-12-14

申请号：US11863528

申请日：2007-09-28

申请人： Stefan Tegen ,  Klaus Muemmler ,  Peter Baars ,  Uta Mierau

发明人： Stefan Tegen ,  Klaus Muemmler ,  Peter Baars ,  Uta Mierau

IPC分类号： H01L21/4763

CPC分类号： H01L21/0274 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76808 ,  H01L21/76816 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned.

摘要翻译： 一种制造集成电路的方法包括在衬底的阵列区域中形成着色焊盘，各个着陆焊盘电耦合到形成在阵列区域中的衬底中的各个器件的部分。 该方法还包括在衬底的周边区域内形成布线。 形成着陆焊盘并形成布线包括在阵列和周边区域均有效的共同光刻工艺。 集成电路的布线和着陆焊盘是自对准的。

公开(公告)号：US07777266B2

公开(公告)日：2010-08-17

申请号：US11947510

申请日：2007-11-29

申请人： Peter Baars ,  Andreas Eifler ,  Klaus Muemmler ,  Stefan Tegen

发明人： Peter Baars ,  Andreas Eifler ,  Klaus Muemmler ,  Stefan Tegen

IPC分类号： H01L29/108

CPC分类号： H01L29/66621 ,  H01L21/76877 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

摘要： An integrated circuit includes a conductive line, the conductive line having a conductive layer made of a metal or a first compound including a metal and a capping layer made of a second compound comprising the metal, the capping layer being in contact with the conductive layer, the first compound being different from the second compound.

摘要翻译： 一种集成电路包括导线，该导线具有由金属构成的导电层或包含金属的第一化合物和由包含金属的第二化合物制成的覆盖层，所述覆盖层与导电层接触， 第一化合物与第二化合物不同。

公开(公告)号：US07566611B2

公开(公告)日：2009-07-28

申请号：US11443652

申请日：2006-05-31

申请人： Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Daniel Koehler ,  Joern Regul

发明人： Peter Baars ,  Klaus Muemmler ,  Stefan Tegen ,  Daniel Koehler ,  Joern Regul

IPC分类号： H01L21/8234

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said memory cell region; removing said mask layer and said first protective layer from said memory cell region; forming a first contact hole between two neighboring gate stacks in said memory cell region, said first contact hole exposing a contact area; forming at least one other contact hole in said peripheral device region, said at least one other contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one other contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：在存储单元区域中提供具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域和外围设备区域上沉积由碳制成的或由含碳材料制成的第一保护层; 在所述存储单元区域中的所述第一保护层上形成掩模层; 通过在蚀刻步骤中去除所述外围设备区域中的所述第一保护层，在所述外围设备区域中暴露所述至少一个栅极堆叠的所述盖，其中所述掩模层用作所述存储单元区域中的掩模; 从所述存储单元区域去除所述掩模层和所述第一保护层; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔，所述第一接触孔暴露接触区域; 在所述外围设备区域中形成至少另一个接触孔，所述至少一个其它接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或位于所述栅极堆叠中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少一个其它接触孔。