公开(公告)号：US06173044B2

公开(公告)日：2001-01-09

申请号：US08595897

申请日：1996-02-06

申请人： Peter Dirk Hortensius ,  Leon Lumelsky ,  Anand Narasimhan

发明人： Peter Dirk Hortensius ,  Leon Lumelsky ,  Anand Narasimhan

IPC分类号： H04M1100

CPC分类号： H04L12/2898 ,  H04L12/2856 ,  H04L12/66 ,  H04M3/487 ,  H04M3/54 ,  H04M7/0009 ,  H04M7/12 ,  H04M11/06 ,  H04M2203/2066 ,  H04Q2213/13093 ,  H04Q2213/13107 ,  H04Q2213/13141 ,  H04Q2213/13196 ,  H04Q2213/13199 ,  H04Q2213/13204 ,  H04Q2213/13389 ,  H04Q2213/13396

摘要： A gateway enables point to multipoint connectivity from voice, data, or SVD clients over voice and data networks. The gateway connects one or more known voice networks (e.g. telephone networks) and one or more data networks (e.g. LANs, WANs, and internet) so that clients on either network may access any of the networks via various devices like analog telephones, data modems, SVD modems, or direct data network connections (e.g., ethernet, token ring). The gateway has connections to both the data network(s) as well as the voice network(s). The gateway is capable of splitting a signal with both voice and data streams and routing either and/or both of these streams over the voice network alone, the data network, or both. A process, executing on the gateway enables the gateway to establish connections on gateway paths and to control and direct a flow of voice and data information between the destinations on these networks.

摘要翻译： 网关通过语音和数据网络实现来自语音，数据或SVD客户端的点对多点连接。 网关连接一个或多个已知的语音网络（例如电话网络）和一个或多个数据网络（例如LAN，WAN和互联网），以使得任一网络上的客户端可以经由诸如模拟电话，数据调制解调器 ，SVD调制解调器或直接数据网络连接（例如，以太网，令牌环）。 网关具有与数据网络以及语音网络的连接。 网关能够分离具有语音和数据流的信号，并且通过语音网络，数据网络或两者在这些流之间路由和/或两者。 在网关上执行的过程使得网关能够在网关路径上建立连接，并且控制和引导这些网络上的目的地之间的语音和数据信息流。

公开(公告)号：US5351067A

公开(公告)日：1994-09-27

申请号：US733766

申请日：1991-07-22

申请人： Leon Lumelsky ,  Sung M. Choi ,  Alan W. Peevers ,  John L. Pittas

发明人： Leon Lumelsky ,  Sung M. Choi ,  Alan W. Peevers ,  John L. Pittas

IPC分类号： G09G5/06 ,  G06T3/00 ,  G06T11/20 ,  G09G5/14 ,  G09G5/36 ,  G09G5/395 ,  H04N5/265 ,  H04N5/272 ,  G09G1/02 ,  G09G1/06

CPC分类号： H04N5/272 ,  G09G5/14 ,  G09G5/395 ,  G09G2340/125

摘要： Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.

摘要翻译： 用于实现提供多个图像的任意混合的光栅图形显示视频数据路径的方法和装置。 视频数据路径是高度并行化的，并且采用在一组查找表的控制下操作的并行设备。 查找表可以从控制器（如主机工作站）加载。 栅格图形显示视频数据路径具有无限的屏幕分辨率，并且还可以从潜在的大量不同的源启用各种不同的像素数据格式。 来自多个图像源的输出在主机工作站的控制下混合，所得到的像素值基于（a）每个图像源的图像的组合半透明系数（α），以及（b）窗口识别号 由主机工作站分配。 将像素值转换为公共预定格式提供了由诸如HDTV和图形服务器之类的多个不同图像源产生的像素值之间的一致性。 为每个源分配单独的帧缓冲区。

公开(公告)号：US5283561A

公开(公告)日：1994-02-01

申请号：US999182

申请日：1992-12-22

申请人： Leon Lumelsky ,  Daniel H. McCabe ,  Alan W. Peevers

发明人： Leon Lumelsky ,  Daniel H. McCabe ,  Alan W. Peevers

IPC分类号： G09G5/14 ,  G09G5/391 ,  H04N9/64 ,  G09G1/06

CPC分类号： H04N9/641 ,  G09G5/14 ,  G09G5/391 ,  G09G2340/125

摘要： A circuit for interfacing between a digital-television circuit for producing pixel data for television images and a computer graphics display permits rapid scaling and positioning of live television images on the graphics display. In a preferred embodiment, the digital-television/computer-graphics interface circuit of the invention includes memory for storing a horizontal-scaling bit pattern and a vertical-scaling bit pattern. Such a preferred interface circuit is adapted to receive digital-television pixel data from the digital television circuit and, on a pixel-by-pixel basis depending on the state of corresponding bits in the horizontal-scaling bit pattern, to skip the pixel in the case of image contraction and to replicate the pixel in the case of image expansion. The preferred interface circuit is also adapted to receive digital-television pixel data on a television-line by television-line basis and, depending on the state of a corresponding bit of the vertical-scaling bit pattern, to skip the entire line of pixel data in the case of image contraction or to replicate the line in the case of image expansion. The interface circuit may include a hardware vector generator for generating scaling bit patterns in accordance with a procedure analogous to a vector-drawing procedure used in graphics displays, such as the "Bresenham procedure."

摘要翻译： 用于产生用于电视图像的像素数据的数字电视电路和计算机图形显示器之间的接口电路允许在图形显示器上快速缩放和定位直播电视图像。 在优选实施例中，本发明的数字电视/计算机 - 图形接口电路包括用于存储水平缩放位模式和垂直缩放位模式的存储器。 这种优选的接口电路适于从数字电视电路接收数字电视像素数据，并且在逐个像素的基础上，取决于水平缩放位模式中的相应位的状态来跳过 图像收缩的情况下，并且在图像扩展的情况下复制像素。 优选的接口电路还适于通过电视线接收电视线上的数字电视像素数据，并且根据垂直缩放位模式的相应比特的状态来跳过像素数据的整个行 在图像收缩的情况下或在图像扩展的情况下复制该行。 接口电路可以包括硬件向量生成器，用于根据类似于在诸如“Bresenham过程”的图形显示中使用的矢量绘制过程的过程产生缩放位模式。

公开(公告)号：US5261049A

公开(公告)日：1993-11-09

申请号：US733906

申请日：1991-07-22

申请人： Leon Lumelsky ,  Sung M. Choi

发明人： Leon Lumelsky ,  Sung M. Choi

IPC分类号： G06F12/06 ,  G06T1/60 ,  G06T9/00 ,  G09G5/00 ,  G09G5/02 ,  G09G5/36 ,  G09G5/393 ,  G09G5/395 ,  H04N1/64 ,  H04N5/907 ,  H04N9/804 ,  H04N9/808 ,  G06F15/20

CPC分类号： H04N1/64 ,  G09G5/02 ,  G09G5/393 ,  G09G5/395 ,  G09G2360/123 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91

摘要： An image buffer semiconductor chip is described that includes circuitry for decompressing, compressed pixel image data such data comprising at least a pair of color codes and a bit mask including bit positions with values that define which pixels in a pixel subset of the pixel image receive the encoded color code data. The chip comprises a matrix of memory modules with the pixels in a pixel subset stored in an interleaved fashion, one pixel per module. A data bus communicates with all of the memory modules and broadcasts the color codes. A mask register stores the bit mask when it appears on the data bus. Circuitry selectively writes a first color code in the modules in accordance with bit values of a first kind in the MASK and writes the second color code into the modules in accordance with bit values of a second kind in the MASK.

公开(公告)号：US5220312A

公开(公告)日：1993-06-15

申请号：US414967

申请日：1989-09-29

申请人： Leon Lumelsky ,  Alan W. Peevers ,  Sung M. Choi

发明人： Leon Lumelsky ,  Alan W. Peevers ,  Sung M. Choi

IPC分类号： G06F3/153 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395

CPC分类号： G09G5/36 ,  G09G5/14 ,  G09G5/395 ,  G09G2340/125

摘要： A locking mechanism is incorporated in a high-resolution video display system including a monitor, a computer for providing controls signals to said display system and two frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

公开(公告)号：US5119082A

公开(公告)日：1992-06-02

申请号：US415012

申请日：1989-09-29

申请人： Leon Lumelsky ,  Sung Min Choi ,  Alan W. Peevers

发明人： Leon Lumelsky ,  Sung Min Choi ,  Alan W. Peevers

IPC分类号： H04N5/66 ,  G06T3/40 ,  G09G5/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  H04N1/393 ,  H04N5/262 ,  H04N7/01

CPC分类号： G06T3/4023 ,  H04N5/2628

摘要： A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor. According to a preferred embodiment of the invention the expansion circuit functions to modify the control signals which controls the read-out of the frame buffer in a predetermined fashion without any additional video buffer storage means.

摘要翻译： 提供了与高分辨率显示系统一起使用的视频像素呈现速率扩展电路。 整体显示系统包括高分辨率监视器，用于提供控制信号的计算机，包括用于存储计算机图形和电视视频图像的高分辨率帧缓冲器，并以由所述控制信号控制的速率读出所述视频数据，并提供所述 数据与高分辨率显示器进行显示。 本发明的扩展电路包括响应于由计算机生成的扩展模式的装置，用于改变从所述帧缓冲器读出的视频像素数据的时基。 电路包括响应于所述扩展模式的装置，用于选择性地重复所述视频显示器的预定扫描线，并且用于选择性地重复沿着给定扫描线的某些像素，以将从所述帧缓冲器读出的视频数据的时基与所述帧缓冲器读出的时基相匹配， 高分辨率显示器。 根据本发明的优选实施例，扩展电路用于修改以预定方式控制帧缓冲器的读出的控制信号，而无需任何附加的视频缓冲存储装置。

公开(公告)号：US4949169A

公开(公告)日：1990-08-14

申请号：US428251

申请日：1989-10-27

申请人： Leon Lumelsky ,  Sung M. Choi ,  Alan W. Peevers

发明人： Leon Lumelsky ,  Sung M. Choi ,  Alan W. Peevers

IPC分类号： H04N7/12 ,  H04M11/00 ,  H04N7/14 ,  H04N11/04 ,  H04N21/2383 ,  H04N21/438

CPC分类号： H04N21/2383 ,  H04N11/04 ,  H04N21/4382 ,  H04N7/148

摘要： An interface architecture for interconnecting a plurality of video display devices together over a high speed digital communication link having limited bandwidth provides at each node for transmitting during a "transmit mode"; (1) sequential pixels of digital data (COMVIDOUT) comprising separate luminance and chrominance fields, from a digital TV source associated with each display node which data represents a scaled video window, (2) the local system clock (SCLK), (3) vertical and horizontal communication sync signals (COMVSOUT and COMSHOUT), (4) luminance and chrominance clock enable signals (COMYOCE and COMCOCE) based on a scaling algorithm utilized in the transmitting video device to insure that both the proper pixels and the proper luminance and chrominance fields associated with these pixels are selected by the communications device for transmission. Further, the interface architecture at each display node provides for receiving during a "receive mode", (5) video input data pixels (COMVIDIN), (6) a video input data clock enable signal from the communications adapter (COMVINCE) which controls the storage of the received video data window in the local frame buffer, (7) horizontal and vertical video input sync signals from the communications adapter (COMHSIN and COMVSIN) for properly synchronizing the storing of the received video input data from the communications adapter into the frame buffer beginning ata predetermined address therein. The system utilizes, to a great extent, exisiting hardware in conventional video display device architectures and associated communications adapters such that a versatile generally applicable transmission system is achievable requiring a minimum of additional control hardware and software.

公开(公告)号：US4903217A

公开(公告)日：1990-02-20

申请号：US13843

申请日：1987-02-12

申请人： Satish Gupta ,  Leon Lumelsky ,  Marc Segre

发明人： Satish Gupta ,  Leon Lumelsky ,  Marc Segre

IPC分类号： G06F12/00 ,  G06F3/153 ,  G06F12/06 ,  G06T1/60 ,  G09G5/39

CPC分类号： G09G5/39 ,  G09G2360/123

摘要： A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. The writing of individual pixels in this array is enabled by energizing the write enable pins to each memory chip directly.The data wires in the memory organization are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same.The frame buffer includes a selectively energizable plane mask for disabling desired planes of accessed pixels.By sequentially controlling the output enables to the different rows of the addressed M by N array, the frame buffer can provide rapid access to N-1 rows after normally accessing the first one.The described architecture will work equally well for M by N other array organizations with a different size (e.g., 8 by 8, 3 by 4, 5 by 4, etc). These other configurations would of course require as many concurrently accessable memory chips or sections as there are pixels in the accessed rectangular array as will be well understood.

公开(公告)号：US4860248A

公开(公告)日：1989-08-22

申请号：US163160

申请日：1988-02-25

申请人： Leon Lumelsky

发明人： Leon Lumelsky

IPC分类号： G06T1/20

CPC分类号： G06T1/20

摘要： A pixel processor includes a plurality of pixel slice processors and the architecture is arranged so that the pixel length is extendible by merely increasing the number of pixel slice processors. Each of the pixel slice processors is firstly interconected with other pixel slice processors, and includes a plurality of registers, gates and multiplexers for selectively presenting to a processing means data derived from a variety of sources, including a frame buffer. The output of the processing means can be stored back in the frame buffer or directed to one or more registers in the associated pixel slice processor or/and to registers in other pixel slice processors. SIMD operation is accomplished for pixel lengths which are equal to or larger than the bit capacity of the pixel slice processors. In a particular embodiment of the invention, SIMD operation is effected on pixel lengths larger than the bit capacity of the pixel slice processors. For operating on k pixels simultaneously, the pixel slice processors are grouped into n/i groups of k processors each, where i indicates the bit handling capacity for each pixel slice processor and n is the pixel length.

摘要翻译： 像素处理器包括多个像素片处理器，并且该架构被布置为使得像素长度仅通过增加像素片处理器的数量来扩展。 每个像素片处理器首先与其他像素片处理器互连，并且包括多个寄存器，门和多路复用器，用于选择地向处理装置呈现包括帧缓冲器的各种源的数据。 处理装置的输出可以被存储在帧缓冲器中或者被定向到相关联的像素片处理器中的一个或多个寄存器或/或其他像素片处理器中的寄存器。 对于等于或大于像素片处理器的位容量的像素长度，实现SIMD操作。 在本发明的特定实施例中，在大于像素片处理器的位容量的像素长度上实现SIMD操作。 为了同时在k个像素上操作，像素片处理器被分组为每个k个处理器的n / i组，其中i表示每个像素片处理器的位处理能力，n是像素长度。

公开(公告)号：US4816814A

公开(公告)日：1989-03-28

申请号：US13848

申请日：1987-02-12

申请人： Leon Lumelsky

发明人： Leon Lumelsky

IPC分类号： G06T11/00 ,  G06T11/20 ,  G09G5/20 ,  G09G5/36 ,  G09G5/393 ,  G09G1/16

CPC分类号： G09G5/393 ,  G09G5/20

摘要： A vector generator for us with an all-points-addressable frame buffer capable of the non-word aligned access, simultaneously, of a square M by N array of pixels providing fast vector drawing independently of vector slope and position in the whole screen area of an attached display monitor. The vector generator utilizes a triangular logic matrix together with a line drawing unit to generate M vector bits lying in an M by N square matrix of the screen of an attached monitor in one memory cycle of the frame buffer and uses the generated matrix to generate a direct mask for the frame buffer whereby the M bit vector may be stored in a single memory cycle.