公开(公告)号：US20180348169A1

公开(公告)日：2018-12-06

申请号：US15773032

申请日：2016-11-04

申请人： Peter Lee ,  Wayne Hall

发明人： Peter Lee ,  Wayne Hall

IPC分类号： G01N29/11 ,  G01N29/04 ,  G01N29/06 ,  G01N29/26 ,  G01N29/28 ,  G01N29/48

CPC分类号： G01N29/11 ,  G01N29/043 ,  G01N29/0645 ,  G01N29/0672 ,  G01N29/069 ,  G01N29/07 ,  G01N29/26 ,  G01N29/262 ,  G01N29/28 ,  G01N29/48 ,  G01N33/46 ,  G01N2291/0238 ,  G01N2291/102 ,  G01N2291/106

摘要： A system for assessment of irregularity in wooden material below the surface of a substrate, from above the surface of the substrate. The wooden material extending from below to above the surface of the substrate and surrounded by the substrate below the surface of the substrate. The system comprising at least one transmitter and receiver or transducer arranged to transmit energy through the material from above the surface of the substrate towards the part of the material below the surface, and to receive energy reflected from the material back through the surface, and a processor arranged to analyse the reflected energy and provide an indication of irregularity in the material below the surface of the substrate.

公开(公告)号：US08999786B1

公开(公告)日：2015-04-07

申请号：US12052573

申请日：2008-03-20

申请人： Albert Wu ,  Pantas Sutardja ,  Winston Lee ,  Peter Lee ,  Chien-Chuan Wei ,  Runzi Chang

发明人： Albert Wu ,  Pantas Sutardja ,  Winston Lee ,  Peter Lee ,  Chien-Chuan Wei ,  Runzi Chang

IPC分类号： H01L21/336 ,  H01L29/788 ,  H01L21/027

CPC分类号： H01L29/41775 ,  H01L21/027 ,  H01L21/823425 ,  H01L27/11568 ,  H01L29/0847 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/792

摘要： Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.

摘要翻译： 公开了具有减小的半导体器件中与栅极间隔的源极接触的晶体管的方法和结构。 在一个实施例中，形成晶体管的方法可以包括：在晶体管的有源区上形成栅极; 形成与有源区域中的栅极对准的源区和漏区; 在源极和漏极区域上形成源极和漏极接触，其中晶体管的栅极至源极接触的间隔小于晶体管的栅极至漏极接触的间隔; 并且使用一个或多个修改的掩模来形成源极区和漏极区的掺杂分布。

公开(公告)号：US08478722B2

公开(公告)日：2013-07-02

申请号：US12945410

申请日：2010-11-12

申请人： Peter Lee ,  Vinod Mehra ,  Rob Woollen

发明人： Peter Lee ,  Vinod Mehra ,  Rob Woollen

IPC分类号： G06F7/00 ,  G06F17/00

CPC分类号： G06F17/30339 ,  G06F17/30082 ,  G06F17/30165 ,  G06F17/30221 ,  G06F17/3023 ,  G06F17/30424 ,  G06F21/6227 ,  G06Q10/10 ,  G06Q30/02 ,  G06Q50/01

摘要： Systems, apparatus, and methods for implementing enterprise level social and business information networking are provided. Users can receive relevant information about a database system and its users at an appropriate time. Users can then use this relevant information to reduce errors and limit redundant efforts. For example, an update of a record in the database can be identified, and a story created automatically about the update and sent to the users that are following the record. Which updates have stories created and which stories are to be sent to which users can be configured. Other events besides updating of records can also be tracked. For example, actions of a user that result in an event can be tracked, where such tracking can also be configurable. Subscriptions to follow an object can be automatic, and access checks can be used to ensure that unauthorized users do not see certain data.

摘要翻译： 提供了实施企业级社会和商业信息网络的系统，设备和方法。 用户可以在适当的时间接收有关数据库系统及其用户的相关信息。 然后，用户可以使用此相关信息来减少错误并限制冗余工作。 例如，可以识别数据库中记录的更新，并自动创建关于更新的故事，并将其发送给跟随记录的用户。 哪些更新创建了故事，哪些故事要发送给哪些用户可以配置。 还可以跟踪除记录更新之外的其他事件。 例如，可以跟踪导致事件的用户的动作，这样的跟踪也可以被配置。 可以自动跟踪对象的订阅，并且可以使用访问检查来确保未经授权的用户看不到某些数据。

公开(公告)号：US08285524B2

公开(公告)日：2012-10-09

申请号：US12608551

申请日：2009-10-29

申请人： Yasuhiro Namba ,  Peter Lee

发明人： Yasuhiro Namba ,  Peter Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A simulation method includes determining a relationship between stress time and a degradation rate of drain current on a basis of a table in which data of a lifetime of a transistor, or the degradation rate of the transistor, is written, and calculating an amount of change in drain current accordance with the degradation rate, using a table in which information indicating a change in the drain current, being dependent on voltage, is written, based on actually measured data of drain current of the transistor after degradation, drain current in an initial state of a particular transistor model, and the relationship between stress time and the degradation rate of drain current.

摘要翻译： 模拟方法包括基于其中写入晶体管的寿命数据或晶体管的劣化速率的数据的表来确定应力时间和漏极电流的劣化率之间的关系，并计算变化量 在根据劣化率的漏极电流中，使用其中写入表示依赖于电压的漏极电流的变化的信息的表，基于在劣化后晶体管的漏极电流的实际测量数据，初始的漏极电流 特定晶体管模型的状态，以及应力时间与漏极电流的劣化率之间的关系。

公开(公告)号：US07888166B2

公开(公告)日：2011-02-15

申请号：US12724266

申请日：2010-03-15

申请人： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Chien-Chuan Wei ,  Winston Lee ,  Peter Lee

发明人： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Chien-Chuan Wei ,  Winston Lee ,  Peter Lee

IPC分类号： H01L21/00 ,  H01L29/18

CPC分类号： H01L27/2463 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.

摘要翻译： 本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。 所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。 还描述了其它实施例。

公开(公告)号：US07801894B1

公开(公告)日：2010-09-21

申请号：US11262283

申请日：2005-10-28

申请人： Jeff G. Bone ,  Laura Arbilla ,  Keith Zoellner ,  Bradley Might ,  Peter Lee

发明人： Jeff G. Bone ,  Laura Arbilla ,  Keith Zoellner ,  Bradley Might ,  Peter Lee

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F17/30091

摘要： A harvester is disclosed for harvesting metadata of managed objects (files and directories) across file systems which are generally not interoperable in an enterprise environment. Harvested metadata may include 1) file system attributes such as size, owner, recency; 2) content-specific attributes such as the presence or absence of various keywords (or combinations of keywords) within documents as well as concepts comprised of natural language entities; 3) synthetic attributes such as mathematical checksums or hashes of file contents; and 4) high-level semantic attributes that serve to classify and categorize files and documents. The classification itself can trigger an action in compliance with a policy rule. Harvested metadata are stored in a metadata repository to facilitate the automated or semi-automated application of policies.

摘要翻译： 披露收割机用于在企业环境中通常不能互操作的文件系统上收集托管对象（文件和目录）的元数据。 收获的元数据可能包括1）文件系统属性，如大小，所有者，新近度; 2）内容特定的属性，例如文档中各种关键字（或关键字的组合）的存在或不存在以及由自然语言实体组成的概念; 3）合成属性，如数学校验和或文件内容的散列; 和4）用于对文件和文档进行分类和分类的高级语义属性。 分类本身可以触发符合策略规则的操作。 收获的元数据存储在元数据存储库中，以便于自动或半自动应用策略。

公开(公告)号：US07745809B1

公开(公告)日：2010-06-29

申请号：US12062444

申请日：2008-04-03

申请人： Pantas Sutardja ,  Albert Wu ,  Chien-Chuan Wei ,  Runzi Chang ,  Winston Lee ,  Peter Lee

发明人： Pantas Sutardja ,  Albert Wu ,  Chien-Chuan Wei ,  Runzi Chang ,  Winston Lee ,  Peter Lee

IPC分类号： H01L29/04

CPC分类号： H01L45/1233 ,  H01L27/0688 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： Embodiments of the present invention provide an apparatus comprising a substrate comprising an emitter layer and at least one emitter interface adjacent to the emitter layer, and a metal protective layer on a top surface of the at least one emitter interface. A method of manufacturing such an apparatus is also disclosed. The method may include performing plasma nitridation directed at column micro-trench strips. Other embodiments are also described.

摘要翻译： 本发明的实施例提供了一种装置，其包括：衬底，其包括发射极层和与发射极层相邻的至少一个发射极接口，以及在所述至少一个发射极接口的顶表面上的金属保护层。 还公开了制造这种装置的方法。 该方法可以包括执行针对柱状微沟槽条带的等离子体氮化。 还描述了其它实施例。

公开(公告)号：US07610285B1

公开(公告)日：2009-10-27

申请号：US11524831

申请日：2006-09-21

申请人： Keith Zoellner ,  Peter Lee ,  Brad Might

发明人： Keith Zoellner ,  Peter Lee ,  Brad Might

IPC分类号： G06F17/30

CPC分类号： G06F17/30705 ,  G06F17/30115 ,  G06F17/3012 ,  Y10S707/99937

摘要： Embodiments of a classification pipeline disclosed herein have the ability to both collect data as it occurs and dynamically redact it, allowing ongoing statistics to be gathered and maintained while simultaneously constraining the total amount of storage capacity that must be dedicated to such a purpose. Various types of information can be extracted from or obtained on the object through the classification pipeline. In one embodiment, the classification pipeline comprises a plurality of layers implemented as a set of services available to network clients through a Web interface or an Applications Programming Interface (API). Each client can subscribe to one or more layers of the classification pipeline at their leisure and tailor their classification pipeline configuration through the interface. The classification pipeline can be configured to collaborate with other software to provide a consistent snapshot of the state of a network environment based on data collected at the time.

摘要翻译： 本文公开的分类流程的实施例具有在数据发生时收集数据的能力，并且动态地对其进行修改，从而允许收集和维护正在进行的统计信息，同时限制必须专用于此目的的总存储容量。 可以通过分类管道从物体中提取或获取各种类型的信息。 在一个实施例中，分类流水线包括通过Web接口或应用编程接口（API）来实现为可用于网络客户端的一组服务的多个层。 每个客户端可以随意订阅分层管道的一层或多层，并通过接口定制其分类流水线配置。 分类流水线可以配置为与其他软件协作，以便根据当时收集的数据提供网络环境状态的一致性快照。

公开(公告)号：US20080246015A1

公开(公告)日：2008-10-09

申请号：US12060792

申请日：2008-04-01

申请人： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Chien-Chuan Wei ,  Winston Lee ,  Peter Lee

发明人： Pantas Sutardja ,  Albert Wu ,  Runzi Chang ,  Chien-Chuan Wei ,  Winston Lee ,  Peter Lee

IPC分类号： H01L45/00

CPC分类号： H01L27/2463 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

摘要： Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described.

摘要翻译： 本发明的实施例提供一种方法，其包括提供包括多个单元的晶片，每个单元包括至少一个发射极。 所述方法还包括在晶片的字线方向上执行平版印刷操作，以形成预热器元件布置，在跨过预热器元件布置的晶片的位线方向上执行平版印刷操作，以形成预加工元件 - 加热器元件，并且跨越预热器元件的一部分在字线方向上执行光刻操作，以形成邻近每个发射器的加热元件。 还描述了其它实施例。

公开(公告)号：US20080205141A1

公开(公告)日：2008-08-28

申请号：US12069637

申请日：2008-02-12

申请人： Peter Lee ,  Fu-Chang Hsu

发明人： Peter Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： H01L29/7887 ,  G11C7/18 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/115 ,  H01L29/7923

摘要： A control apparatus programs, reads, and erases trapped charges representing multiple data bits from a charge trapping region of a NMOS dual-sided charge-trapping nonvolatile memory cell includes a programming circuit, an erasing circuit, and a reading circuit. The programming circuit provides a negative medium large program voltage to cell's gate along with positive drain and source voltage to inject hot carriers of holes to two charge trapping regions, one of a plurality of threshold adjustment voltages representing a portion of the multiple data bits to the drain and source regions to set the hot carrier charge levels to the two charge trapping regions. The erasing circuit provides a very large positive erase voltage to tunnel the electrons from cell's channel to whole trapping layer including the two charge trapping regions. The reading circuit generates one of a plurality of threshold detection voltages to detect one of a plurality of programmed threshold voltages representative of multiple data bits, generates a drain voltage level to activate the charge-trapping nonvolatile memory cell.

摘要翻译： 控制装置对来自NMOS双侧电荷捕获非易失性存储单元的电荷捕获区域的多个数据位进行编程，读取和擦除捕获的电荷包括编程电路，擦除电路和读取电路。 编程电路向单元的栅极提供负的中等大的编程电压以及正的漏极和源极电压，以将空穴的热载流子注入到两个电荷俘获区域，多个阈值调整电压中的一个表示多个数据位的一部分 漏极和源极区域，以将热载流子电荷电平设置为两个电荷捕获区域。 擦除电路提供非常大的正擦除电压，以将电子从电池的通道隧穿到包括两个电荷俘获区域的整个俘获层。 读取电路产生多个阈值检测电压中的一个，以检测表示多个数据位的多个编程的阈值电压中的一个，产生漏极电压电平以激活电荷捕获非易失性存储单元。