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公开(公告)号：US20140036590A1
公开(公告)日：2014-02-06
申请号：US13564458
申请日：2012-08-01
申请人： Peter Sean Feeley , Koji Sakui , Akira Goda
发明人： Peter Sean Feeley , Koji Sakui , Akira Goda
IPC分类号： G11C16/04
摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
摘要翻译： 公开了诸如包括包含电荷存储装置串的存储器单元块的方法和装置。 每个串可以包括以多层形成的多个电荷存储装置。 该装置可以包括由串共享的多个接入线。 多个接入线路中的每一个可以耦合到与多个层级的相应层对应的电荷存储装置。 该装置可以包括与弦相关联的多个子源。 多个子源中的每一个可以耦合到字符串的多个子集的相应子集的每个串的源选择门，并且每个子源可以独立地从其他子源中选择以选择字符串 独立于对应于其他子集的其他字符串。
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公开(公告)号：US10541029B2
公开(公告)日：2020-01-21
申请号：US13564458
申请日：2012-08-01
申请人： Peter Sean Feeley , Koji Sakui , Akira Goda
发明人： Peter Sean Feeley , Koji Sakui , Akira Goda
摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
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公开(公告)号：US20130336070A1
公开(公告)日：2013-12-19
申请号：US13525035
申请日：2012-06-15
申请人： Koji Sakui , Peter Sean Feeley
发明人： Koji Sakui , Peter Sean Feeley
IPC分类号： G11C16/10 , H01L29/788
CPC分类号： G11C16/10 , G11C16/02 , G11C16/0466 , G11C16/0483
摘要： Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.
摘要翻译： 公开了诸如包括多个电荷存储装置串的块的每个串，包括与柱相关联的多个电荷存储装置，并且每个支柱包括半导体材料。 公开了一种方法，例如包括在与块中的柱相关联的第一电荷存储装置上执行第一操作的方法，修改支柱的电位，以及对块中的第二电荷存储装置执行第二操作 。 描述附加的装置和方法。
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公开(公告)号：US09171625B2
公开(公告)日：2015-10-27
申请号：US13525035
申请日：2012-06-15
申请人： Koji Sakui , Peter Sean Feeley
发明人： Koji Sakui , Peter Sean Feeley
CPC分类号： G11C16/10 , G11C16/02 , G11C16/0466 , G11C16/0483
摘要： Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.
摘要翻译： 公开了诸如包括多个电荷存储装置串的块的每个串，包括与柱相关联的多个电荷存储装置，并且每个支柱包括半导体材料。 公开了一种方法，例如包括在与块中的柱相关联的第一电荷存储装置上执行第一操作的方法，修改支柱的电位，以及对块中的第二电荷存储装置执行第二操作 。 描述附加的装置和方法。
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公开(公告)号：US08356216B2
公开(公告)日：2013-01-15
申请号：US13346538
申请日：2012-01-09
IPC分类号： G11C29/00
CPC分类号： G06F11/006 , G06F11/106
摘要： Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
摘要翻译： 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分以用于潜在错误的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。
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公开(公告)号：US20100313077A1
公开(公告)日：2010-12-09
申请号：US12846629
申请日：2010-07-29
IPC分类号： G06F11/26
CPC分类号： G06F11/006 , G06F11/106
摘要： Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
摘要翻译： 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分以用于潜在错误的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。
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公开(公告)号：US20190065108A1
公开(公告)日：2019-02-28
申请号：US15693121
申请日：2017-08-31
申请人： Michael G. Miller , Kishore Kumar Muchherla , Harish Singidi , Sampath Ratnam , Renan Padilla , Gary F. Besinga , Peter Sean Feeley
发明人： Michael G. Miller , Kishore Kumar Muchherla , Harish Singidi , Sampath Ratnam , Renan Padilla , Gary F. Besinga , Peter Sean Feeley
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0679 , G11C5/144 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/30 , G11C16/3459
摘要： Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
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公开(公告)号：US20190066802A1
公开(公告)日：2019-02-28
申请号：US15689747
申请日：2017-08-29
申请人： Ashutosh Malshe , Kishore Kumar Muchhert , Harish Singidi , Peter Sean Feeley , Sampath Ratnam , kulachet Tanpairoj , Ting Luo
发明人： Ashutosh Malshe , Kishore Kumar Muchhert , Harish Singidi , Peter Sean Feeley , Sampath Ratnam , kulachet Tanpairoj , Ting Luo
CPC分类号： G11C16/26 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/28 , G11C16/349 , G11C29/021 , G11C29/028 , G11C2207/2254
摘要： Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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公开(公告)号：US08095835B2
公开(公告)日：2012-01-10
申请号：US12846629
申请日：2010-07-29
IPC分类号： G11C29/00
CPC分类号： G06F11/006 , G06F11/106
摘要： Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
摘要翻译： 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分以用于潜在错误的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。
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公开(公告)号：US07770079B2
公开(公告)日：2010-08-03
申请号：US11843466
申请日：2007-08-22
IPC分类号： G11C29/00
CPC分类号： G06F11/006 , G06F11/106
摘要： Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
摘要翻译： 各种实施例包括当满足扫描条件时扫描存储器件的至少一部分以用于潜在错误的方法，装置和系统。 条件可以取决于多个读取操作，多个写入操作，时间等中的一个或多个。 公开了包括附加方法，装置和系统的其它实施例。
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