公开(公告)号：US4112362A

公开(公告)日：1978-09-05

申请号：US755619

申请日：1976-12-30

申请人： Philip L. Hower ,  William G. Carlson ,  Tapan K. Gupta

发明人： Philip L. Hower ,  William G. Carlson ,  Tapan K. Gupta

IPC分类号： G01R31/12 ,  G01R15/00 ,  G01R31/00 ,  G01R31/16 ,  G01R31/02

CPC分类号： G01R31/00 ,  G01R15/00

摘要： A method for the nondestructive testing of voltage limiting blocks includes the steps of providing several discrete electrical contacts across the block, sequentially applying to each of the contacts a voltage to determine the corresponding current and utilizing the current and voltage values to determine constants related to the microstructure of that particular location. The constants can then be utilized to derive a contour map which will be indicative of a hot spot in such block as determined by a maxima of the contour map.

摘要翻译： 用于电压限制块的非破坏性测试的方法包括以下步骤：在块上提供几个离散的电触点，顺序地向每个触点施加电压以确定相应的电流并利用电流和电压值来确定与 该特定位置的微观结构。 然后可以使用常数来导出轮廓图，其将指示由等高线图的最大值确定的这种块中的热点。

公开(公告)号：US20120112277A1

公开(公告)日：2012-05-10

申请号：US13284011

申请日：2011-10-28

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

公开(公告)号：US20110073955A1

公开(公告)日：2011-03-31

申请号：US12962159

申请日：2010-12-07

申请人： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

发明人： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

IPC分类号： H01L27/06

CPC分类号： H01L21/8249 ,  H01L21/76232 ,  H01L27/0623

摘要： A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.

摘要翻译： 一种半导体器件，包括在半导体衬底（115）上或半导体衬底（115）中的第一晶体管器件（130）和衬底上或衬底中的第二晶体管器件（132）。 该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽（200）。 绝缘沟槽的至少一个上角（610）是衬底的横向平面（620）中的圆角。

公开(公告)号：US4042947A

公开(公告)日：1977-08-16

申请号：US646794

申请日：1976-01-06

申请人： Chang K. Chu ,  Philip L. Hower ,  George W. Vomish

发明人： Chang K. Chu ,  Philip L. Hower ,  George W. Vomish

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/72

CPC分类号： H01L29/41708 ,  H01L29/0804 ,  H01L29/732

摘要： A transistor device is described in which an NPN semiconductor structure has a specially adapted N-type emitter zone and associated electrode. The emitter zone is produced by etching a cavity in one major surface of the semiconductor body followed by diffusion of N-type dopant material. Emitter, base and collector electrodes are then affixed to the appropriate surfaces of the body to provide electrical and thermal contact thereto.

摘要翻译： 描述了一种晶体管器件，其中NPN半导体结构具有特别适合的N型发射极区和相关电极。 通过蚀刻半导体主体的一个主表面中的空腔，然后N型掺杂剂材料的扩散来产生发射极区。 然后将发射极，基极和集电极固定到主体的适当表面以提供与其的电接触和热接触。

公开(公告)号：US09806190B2

公开(公告)日：2017-10-31

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/12 ,  H01L29/10 ,  H01L29/861 ,  H01L27/06

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

公开(公告)号：US08853029B2

公开(公告)日：2014-10-07

申请号：US13188162

申请日：2011-07-21

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.

摘要翻译： 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

公开(公告)号：US08728846B2

公开(公告)日：2014-05-20

申请号：US12544548

申请日：2009-08-20

申请人： Barry Jon Male ,  Philip L. Hower

发明人： Barry Jon Male ,  Philip L. Hower

IPC分类号： H01L29/66

CPC分类号： H01L35/30 ,  H01L23/38 ,  H01L27/16 ,  H01L35/22 ,  H01L35/32 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

摘要翻译： 公开了一种热电装置，其包括从IC的顶表面突出的金属热端子，其连接到由IC的互连元件制成的垂直导热导管。 侧向热电元件在一端连接到垂直导管，并在另一端与IC基板相互散热。 侧向热电元件通过顶侧的互连电介质材料和底侧的场氧化物热隔离。 当在发电机模式下工作时，金属热端子连接到热源，并且IC基板连接到散热器。 热功率流过垂直管道到横向热电元件，产生电位。 电位可以施加到IC中的元件或电路。 热电装置可以集成到IC中而不增加制造成本或复杂性。

公开(公告)号：US20120104497A1

公开(公告)日：2012-05-03

申请号：US13282305

申请日：2011-10-26

申请人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

发明人： Marie Denison ,  Philip L. Hower ,  Sameer Pendharkar

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7824 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/1087 ,  H01L29/7818 ,  H01L29/7835 ,  H01L29/861

摘要： An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) so that the drain or body region is coupled to the handle wafer through a p-n junction. An integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel) coupled to the handle wafer through a p-n junction, that is electrically isolated from the drain or body region. A process of forming an integrated circuit on an SOI substrate containing an extended drain MOS transistor with a through substrate diode in a drain (n-channel) or body region (p-channel).

摘要翻译： SOI衬底上的集成电路，其包含在漏极（n沟道）或体区（p沟道）中具有穿通衬底二极管的扩展漏极MOS晶体管，使得漏极或体区域通过pn耦合到处理晶片 交界处 在SOI衬底上的集成电路，其包含通过pn结耦合到处理晶片的漏极（n沟道）或体区（p沟道）中的贯穿衬底二极管的延伸漏极MOS晶体管，其与 排水或身体区域。 在包含漏极（n沟道）或体区（p沟道）中的贯通衬底二极管的延伸漏极MOS晶体管的SOI衬底上形成集成电路的工艺。

公开(公告)号：US07910417B2

公开(公告)日：2011-03-22

申请号：US12176488

申请日：2008-07-21

申请人： Philip L. Hower ,  David A. Walch ,  John Lin ,  Steven L. Merchant

发明人： Philip L. Hower ,  David A. Walch ,  John Lin ,  Steven L. Merchant

IPC分类号： H01L21/337

CPC分类号： H01L29/808 ,  H01L29/1066

摘要： A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

摘要翻译： 结型场效应晶体管（JFET）可以制造具有阱区，阱区包括平均掺杂剂浓度基本上小于阱区的剩余部分的平均掺杂浓度的沟道区。 与阱区域的其余部分相比，沟道区域的较低平均掺杂浓度降低了JFET的夹断电压。

公开(公告)号：US06624481B1

公开(公告)日：2003-09-23

申请号：US10407037

申请日：2003-04-04

申请人： Sameer P. Pendharkar ,  Philip L. Hower ,  Robert Steinhoff

发明人： Sameer P. Pendharkar ,  Philip L. Hower ,  Robert Steinhoff

IPC分类号： H01L2362

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).

摘要翻译： 包括第一和第二双极元件（210,220）的ESD坚固的双极晶体管（200），其中第一双极元件（210）的第一触发电压接近第二双极元件（220）的第二维持电压。 第一和第二双极元件（210,220）分别包括第一和第二基极（214,224），发射极（216,226）和集电极（212,222）。 耦合第一和第二基极（214,224），并且耦合第一和第二集电极（212,222）。 ESD稳健双极晶体管（200）还包括发射极电阻（250）和基极电阻（260），其中发射极电阻（250）将第一和第二发射极（216,226）和基极电阻（260）耦合 第二发射器（226）和第一和第二基极（214,224）。