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公开(公告)号：US08438419B2
公开(公告)日：2013-05-07
申请号：US12997993
申请日：2008-06-30
IPC分类号： H04L29/14
CPC分类号： H04L12/403 , H01L2224/48137 , H01L2224/49175 , H01L2924/13091 , H04L12/10 , H04L25/0272 , H04L25/028 , H04L25/08 , H01L2924/00
摘要： A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.
摘要翻译： 差分通信总线包括主模块和连接到至少第一和第二导体的多个从模块，从而在主模块和从模块之间进行通信。 主模块包括用于将第一和第二电压分别施加到第一和第二导体并用于在第一和第二导体中的电流和吸收电流的驱动器。 驱动器控制第一和第二电压之间的差异以及第一和第二电压的共模值。 该驱动器包括用于限制第一和第二导体中的电流的第一采样和吸收限流器以及第二采集和吸收限流器。 主模块选择性地响应于触发同时激活第一和第二源电流限制器或第一和第二吸收电流限制器的故障条件以禁用驱动器。
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公开(公告)号：US08612657B2
公开(公告)日：2013-12-17
申请号：US13059084
申请日：2008-08-22
IPC分类号： G06F13/00 , G06F13/364
CPC分类号： G06F13/364 , H04L12/403 , H04L25/4902 , H04L2012/40273
摘要： Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.
摘要翻译： 用于通过在脉冲宽度调制信号形式的电母线上产生主逻辑信号在电母线上进行通信的方法和装置。 以电流信号的形式在电气总线上产生从属逻辑信号。 通过对电气总线上的电流信号的大小进行采样来读取从属逻辑信号，其中当总线上的电压保持恒定一段时间时，电气总线上的电流大小在位时间的某一点被采样 比在比特时间期间电压保持在任何电平的最短时间。
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3.发明授权Buffer apparatus, integrated circuit and method of reducing a portion of an oscillation of an output signal 有权缓冲装置，集成电路和减少输出信号振荡的一部分的方法公开(公告)号：US08193828B2
公开(公告)日：2012-06-05
申请号：US13056334
申请日：2008-07-31
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00361 , H03K17/167 , H03K2217/94094
摘要： A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
摘要翻译： 用于通信总线的缓冲装置包括具有输出的驱动器电路。 具有输入的放大器电路耦合到驱动器电路的输出端。 驱动器电路被布置成在使用时产生具有包括其中的步骤的波形的驱动信号，以便基本上抑制放大器电路产生输出信号的振荡的一部分。
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公开(公告)号：US20110138090A1
公开(公告)日：2011-06-09
申请号：US13059084
申请日：2008-08-22
IPC分类号： G06F13/00
CPC分类号： G06F13/364 , H04L12/403 , H04L25/4902 , H04L2012/40273
摘要： Method and apparatus for communicating on an electrical bus by generating a master logical signal on the electrical bus in the form of a pulse-width modulation signal. Generating a slave logical signal on the electrical bus in the form of a current signal. Reading the slave logical signal by sampling the magnitude of the current signal on the electrical bus, wherein magnitude of the current on the electrical bus is sampled at a point in the bit time when the voltage on the electrical bus has remained constant for a period longer than the shortest time that the voltage remains at any level during the bit time.
摘要翻译： 用于通过在脉冲宽度调制信号形式的电母线上产生主逻辑信号在电母线上进行通信的方法和装置。 以电流信号的形式在电气总线上产生从属逻辑信号。 通过对电气总线上的电流信号的大小进行采样来读取从属逻辑信号，其中当总线上的电压保持恒定一段时间时，电气总线上的电流大小在位时间的某一点被采样 比在比特时间期间电压保持在任何电平的最短时间。
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5.发明申请BUFFER APPARATUS, INTEGRATED CIRCUIT AND METHOD OF REDUCING A PORTION OF AN OSCILLATION OF AN OUTPUT SIGNAL 有权缓冲器装置，集成电路和减少输出信号振荡部分的方法公开(公告)号：US20110121858A1
公开(公告)日：2011-05-26
申请号：US13056334
申请日：2008-07-31
IPC分类号： H03K19/0175
CPC分类号： H03K19/00361 , H03K17/167 , H03K2217/94094
摘要： A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
摘要翻译： 用于通信总线的缓冲装置包括具有输出的驱动器电路。 具有输入的放大器电路耦合到驱动器电路的输出端。 驱动器电路被布置成在使用时产生具有包括其中的步骤的波形的驱动信号，以便基本上抑制放大器电路产生输出信号的振荡的一部分。
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公开(公告)号：US20110093739A1
公开(公告)日：2011-04-21
申请号：US12997993
申请日：2008-06-30
CPC分类号： H04L12/403 , H01L2224/48137 , H01L2224/49175 , H01L2924/13091 , H04L12/10 , H04L25/0272 , H04L25/028 , H04L25/08 , H01L2924/00
摘要： A differential communication bus comprising a master module and a plurality of slave modules connected to at least first and second conductors whereby to communicate between the master and slave modules. The master module comprises a driver for applying first and second voltages respectively to the first and second conductors and for sourcing and sinking currents in the first and second conductors. The driver controls a difference between the first and second voltages and a common mode value of the first and second voltages. The driver includes first sourcing and sinking current limiters and second sourcing and sinking current limiters for limiting the currents in the first and second conductors. The master module is selectively responsive to a fault condition triggering simultaneous activation of the first and second sourcing current limiters or of the first and second sinking current limiters to disable the driver.
摘要翻译： 差分通信总线包括主模块和连接到至少第一和第二导体的多个从模块，从而在主模块和从模块之间进行通信。 主模块包括用于将第一和第二电压分别施加到第一和第二导体并用于在第一和第二导体中的电流和吸收电流的驱动器。 驱动器控制第一和第二电压之间的差异以及第一和第二电压的共模值。 该驱动器包括用于限制第一和第二导体中的电流的第一采样和吸收限流器以及第二采集和吸收限流器。 主模块选择性地响应于触发同时激活第一和第二源电流限制器或第一和第二吸收电流限制器的故障条件以禁用驱动器。
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公开(公告)号：US20160290804A1
公开(公告)日：2016-10-06
申请号：US15035869
申请日：2013-11-22
IPC分类号： G01C19/5726 , H04L7/033 , G06F1/08
CPC分类号： G01C19/5726 , G01C19/04 , G06F1/08 , G06F1/1694 , H04L7/033 , H04L7/06
摘要： A vibration gyroscope circuitry (VCIRC) connectable to a vibrating MEMS gyroscope (VMEMS). The circuitry comprises drive circuitry (DRIVE) arranged to drive, when the circuitry is connected, the vibration MEMS gyroscope (VMEMS) and a measurement unit (DMU) which provides a drive measurement voltage signal (DMV) forming a measure of a displacement of a mass along a drive axis. A sense circuitry (SENSE) is arranged to process a sense measurement signal of the vibration MEMS gyroscope (VMEMS) forming a measure for a displacement of the mass along a sense axis. A digital sample clock generator (SCG) is arranged to generate a sample clock signal (SCLK) from an input signal (FDxy) derivable from a drive measurement voltage signal (DMV). The sample clock generator (SCG) comprises an oscillator (HFOSC) arranged to generate a master clock (MOSC), and a counter unit (OSCCNTR) arranged to count master clock periods during one period of the input signal. The clock generator also comprises a number count monitor (NCM) arranged to determine during how many input signal periods the number count stays constant, and to compare the number of constant periods (Ncp) with a critical number of constant periods (Ncp_crit). A frequency shifter (FSH) will trigger the oscillator to shift the master clock frequency whenever the number count monitor (NCM) has determined that the number of constant periods (Ncp) exceeds the critical number of constant periods (Ncp_crit).
摘要翻译： 振动陀螺仪电路（VCIRC）可连接到振动MEMS陀螺仪（VMEMS）。 电路包括驱动电路（DRIVE），驱动电路（DRIVE）被布置成在电路连接时驱动振动MEMS陀螺仪（VMEMS）和测量单元（DMU），其提供驱动测量电压信号（DMV），其形成一个 沿驱动轴的质量。 感测电路（SENSE）被布置为处理振动MEMS陀螺仪（VMEMS）的感测测量信号，其形成沿着感测轴的质量位移的测量。 数字采样时钟发生器（SCG）被布置成从可从驱动测量电压信号（DMV）导出的输入信号（FDxy）产生采样时钟信号（SCLK）。 采样时钟发生器（SCG）包括布置成产生主时钟（MOSC）的振荡器（HFOSC）和被配置为在输入信号的一个周期期间对主时钟周期进行计数的计数器单元（OSCCNTR）。 时钟发生器还包括一个数字计数监视器（NCM），用于确定在数量保持不变的多少个输入信号周期内，以及将常数周期数（Ncp）与临界数量的恒定周期（Ncp_crit）进行比较。 每当数字监视（NCM）确定恒定周期数（Ncp）超过常数周期（Ncp_crit）的临界数时，移频器（FSH）将触发振荡器来移动主时钟频率。
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公开(公告)号：US20130187719A1
公开(公告)日：2013-07-25
申请号：US12936214
申请日：2008-04-18
IPC分类号： H03L7/16
CPC分类号： H03L7/16 , H03B5/1228 , H03B2201/0208 , H03L7/099 , H03L7/113 , H03L7/18
摘要： A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
摘要翻译： 一种锁相环系统，包括：压控振荡器电路，包括第一多个可切换变容二极管，用于选择VCO的频带，其具有随频带变化的增益;以及第二多个可切换变容二极管，用于改变 在所选频段的增益。 PLL系统具有PLL反馈电路，其包括用于将反馈电路切换到开环状态的开关装置，其中多个预定调谐电压可以施加到VCO; 用于测量合成VCO频率的频率测量装置; 以及控制单元，用于确定相对于合成频率和调谐电压的增益。
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9.发明授权Methods and apparatus for detecting out-of-range signals in an analog-to-digital converter 有权用于在模拟 - 数字转换器中检测超出范围信号的方法和装置公开(公告)号：US06741194B1
公开(公告)日：2004-05-25
申请号：US10328360
申请日：2002-12-23
IPC分类号： H03M106
CPC分类号： H03M1/183 , H03M1/0695 , H03M1/129 , H03M1/187 , H03M1/44
摘要： An analog-to-digital (A/D) converter suitable for use with redundant signed digit (RSD) coverter stages is provided with an out-of-range (OOR) detection circuit. If an out-of-range input signal is detected, the detection circuit identifies the OOR condition so that the converter can take remedial action. Examples of remedial action may include adjusting the gain of one or more converter stages, adjusting the analog input signal provided to one or more converter stages, and/or adjusting the digital output of the converter to reflect the OOR condition. The ORR detection circuit may receive its input from a converter stage that is distinct from the stage providing the most significant bit (MSB) of the digital output to preserve the resolution of the most significant bit.
摘要翻译： 适用于冗余有符号数字（RSD）覆盖器级的模拟（A / D）转换器提供超范围（OOR）检测电路。 如果检测到超出范围的输入信号，则检测电路识别OOR条件，以便转换器可以采取补救措施。 补救措施的示例可以包括调整一个或多个转换器级的增益，调整提供给一个或多个转换器级的模拟输入信号和/或调整转换器的数字输出以反映OOR条件。 ORR检测电路可以从与提供数字输出的最高有效位（MSB）的级不同的转换器级接收其输入，以保持最高有效位的分辨率。
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公开(公告)号：US08912857B2
公开(公告)日：2014-12-16
申请号：US12936214
申请日：2008-04-18
CPC分类号： H03L7/16 , H03B5/1228 , H03B2201/0208 , H03L7/099 , H03L7/113 , H03L7/18
摘要： A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
摘要翻译： 一种锁相环系统，包括：压控振荡器电路，包括第一多个可切换变容二极管，用于选择VCO的频带，其具有随频带变化的增益;以及第二多个可切换变容二极管，用于改变 在所选频段的增益。 PLL系统具有PLL反馈电路，其包括用于将反馈电路切换到开环状态的开关装置，其中多个预定调谐电压可以施加到VCO; 用于测量合成VCO频率的频率测量装置; 以及控制单元，用于确定相对于合成频率和调谐电压的增益。
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