公开(公告)号：US11444696B2

公开(公告)日：2022-09-13

申请号：US14326364

申请日：2014-07-08

Applicant: PhotonIC International Pte. Ltd.

Inventor： Birendra Dutt ,  Ashok Kapoor ,  Weiwei Song ,  Raj Rajasekharan

IPC: H04B10/00 ,  H04B10/40 ,  H04B10/50 ,  H04J14/02 ,  G02B6/293 ,  H04B10/66 ,  G02B6/12 ,  G02B6/42 ,  G02B6/43 ,  G02F1/01 ,  G02F1/025 ,  H04B10/516

Abstract: Various embodiments of a micro-disc modulator as well as a silicon photonic device and an optoelectronic communication apparatus using the micro-disc modulator are described. In one aspect, a device includes a SOI substrate and a silicon photonic structure formed on a primary surface of the SOI substrate. The semiconductor substrate includes a silicon waveguide and a micro-disc modulator. The micro-disc modulator is adjacent to the silicon waveguide and has a top surface substantially parallel to the primary surface of the SOI substrate. The top surface of the micro-disc modulator includes one or more discontinuities therein. The micro-disc modulator may be a multi junction micro-disc modulator having two vertical p-n junctions with a single resonance frequency to achieve high-speed modulation and low-power consumption.

公开(公告)号：US20160314091A1

公开(公告)日：2016-10-27

申请号：US14822766

申请日：2015-08-10

Applicant: PhotonIC International Pte. Ltd.

Inventor： Birendra Dutt ,  Douglas B. Boyle

IPC: G06F13/42 ,  G06F13/20

CPC classification number: G06F12/0842 ,  G06F1/06 ,  G06F1/10 ,  G06F9/44505 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/1027 ,  G06F13/20 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/781 ,  G06F15/7825 ,  G06F2212/283 ,  G06F2212/622 ,  G06F2212/681 ,  G06F2212/70 ,  G11C7/1072 ,  G11C14/0018

Abstract: A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.

公开(公告)号：US09495295B1

公开(公告)日：2016-11-15

申请号：US14822778

申请日：2015-08-10

Applicant: PhotonIC International Pte. Ltd.

Inventor： Birendra Dutt ,  Douglas B. Boyle

IPC: G06F12/08 ,  G11C7/10 ,  G06F15/78

CPC classification number: G06F12/0842 ,  G06F1/06 ,  G06F1/10 ,  G06F9/44505 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/1027 ,  G06F13/20 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/781 ,  G06F15/7825 ,  G06F2212/283 ,  G06F2212/622 ,  G06F2212/681 ,  G06F2212/70 ,  G11C7/1072 ,  G11C14/0018

Abstract: A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.

Abstract translation: 光子学优化的多处理器系统可以包括多个处理器芯片，每个处理器芯片包括至少一个输入/输出（I / O）组件。 多处理器系统还可以包括第一和第二光子组件。 至少一个处理器芯片的至少一个I / O分量可以被配置为直接驱动第一光子分量并从第二光子分量接收信号。 从任何一个处理器芯片到任何全局存储器位置处的数据的总等待时间可能不受到往返光速传播延迟的支配。 许多处理器芯片可以至少为10,000，并且处理器芯片可以被封装成不超过8m 3的总体积。 处理器芯片的密度可以大于每立方米1,000个芯片。

公开(公告)号：US20160314088A1

公开(公告)日：2016-10-27

申请号：US14822758

申请日：2015-08-10

Applicant: PhotonIC International Pte. Ltd.

Inventor： Birendra Dutt ,  Douglas B. Boyle

IPC: G06F13/40 ,  G11C7/10 ,  G06F15/78 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/42 ,  G11C14/00

CPC classification number: G06F12/0842 ,  G06F1/06 ,  G06F1/10 ,  G06F9/44505 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/1027 ,  G06F13/20 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/781 ,  G06F15/7825 ,  G06F2212/283 ,  G06F2212/622 ,  G06F2212/681 ,  G06F2212/70 ,  G11C7/1072 ,  G11C14/0018

Abstract: A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.

公开(公告)号：US20160313760A1

公开(公告)日：2016-10-27

申请号：US14822752

申请日：2015-08-10

Applicant: PhotonIC International Pte. Ltd.

Inventor： Birendra Dutt ,  Douglas B. Boyle

IPC: G06F1/10 ,  G06F1/06

CPC classification number: G06F12/0842 ,  G06F1/06 ,  G06F1/10 ,  G06F9/44505 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/1027 ,  G06F13/20 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/781 ,  G06F15/7825 ,  G06F2212/283 ,  G06F2212/622 ,  G06F2212/681 ,  G06F2212/70 ,  G11C7/1072 ,  G11C14/0018

Abstract: A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.

Abstract translation: 光子学优化的多处理器系统可以包括多个处理器芯片，每个处理器芯片包括至少一个输入/输出（I / O）组件。 多处理器系统还可以包括第一和第二光子组件。 至少一个处理器芯片的至少一个I / O分量可以被配置为直接驱动第一光子分量并从第二光子分量接收信号。 从任何一个处理器芯片到任何全局存储器位置处的数据的总等待时间可能不受到往返光速传播延迟的支配。 许多处理器芯片可以至少为10,000，并且处理器芯片可以被封装成不超过8m 3的总体积。 处理器芯片的密度可以大于每立方米1,000个芯片。

公开(公告)号：US20160314070A1

公开(公告)日：2016-10-27

申请号：US14822778

申请日：2015-08-10

Applicant: PhotonIC International Pte. Ltd.

Inventor： Birendra Dutt ,  Douglas B. Boyle

IPC: G06F12/08 ,  G06F15/78 ,  G11C7/10

CPC classification number: G06F12/0842 ,  G06F1/06 ,  G06F1/10 ,  G06F9/44505 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/1027 ,  G06F13/20 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/781 ,  G06F15/7825 ,  G06F2212/283 ,  G06F2212/622 ,  G06F2212/681 ,  G06F2212/70 ,  G11C7/1072 ,  G11C14/0018

Abstract: A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.

公开(公告)号：US20160314003A1

公开(公告)日：2016-10-27

申请号：US14822744

申请日：2015-08-10

Applicant: PhotonIC International Pte. Ltd.

Inventor： Birendra Dutt ,  Douglas B. Boyle

IPC: G06F9/445 ,  G06F13/40

CPC classification number: G06F12/0842 ,  G06F1/06 ,  G06F1/10 ,  G06F9/44505 ,  G06F12/0246 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/1027 ,  G06F13/20 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/781 ,  G06F15/7825 ,  G06F2212/283 ,  G06F2212/622 ,  G06F2212/681 ,  G06F2212/70 ,  G11C7/1072 ,  G11C14/0018

Abstract: A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m3. A density of the processor chips may be greater than 1,000 chips per cubic meter.

公开(公告)号：US20160013865A1

公开(公告)日：2016-01-14

申请号：US14326364

申请日：2014-07-08

Applicant: PhotonIC International Pte. Ltd.

Inventor： Birendra Dutt ,  Ashok Kapoor ,  Weiwei Song ,  Raj Rajasekharan

IPC: H04B10/40 ,  G02F1/01 ,  H04B10/50 ,  G02B6/43 ,  H04B10/516 ,  G02F1/025 ,  G02B6/42

CPC classification number: H04B10/40 ,  G02B6/12007 ,  G02B6/29341 ,  G02B6/4295 ,  G02B6/43 ,  G02F1/0147 ,  G02F1/025 ,  G02F2201/18 ,  G02F2202/105 ,  G02F2203/055 ,  G02F2203/15 ,  G02F2203/69 ,  H04B10/50 ,  H04B10/501 ,  H04B10/516 ,  H04B10/66 ,  H04J14/02

Abstract: Various embodiments of a micro-disc modulator as well as a silicon photonic device and an optoelectronic communication apparatus using the micro-disc modulator are described. In one aspect, a device includes a SOI substrate and a silicon photonic structure formed on a primary surface of the SOI substrate. The semiconductor substrate includes a silicon waveguide and a micro-disc modulator. The micro-disc modulator is adjacent to the silicon waveguide and has a top surface substantially parallel to the primary surface of the SOI substrate. The top surface of the micro-disc modulator includes one or more discontinuities therein. The micro-disc modulator may be a multi junction micro-disc modulator having two vertical p-n junctions with a single resonance frequency to achieve high-speed modulation and low-power consumption.

Abstract translation: 描述了微盘调制器以及硅光子器件和使用微盘调制器的光电通信装置的各种实施例。 在一个方面，一种器件包括形成在SOI衬底的主表面上的SOI衬底和硅光子结构。 半导体衬底包括硅波导和微盘调制器。 微盘调制器与硅波导相邻，并且具有基本上平行于SOI衬底的主表面的顶表面。 微盘调制器的顶表面包括其中的一个或多个不连续性。 微盘调制器可以是具有具有单个谐振频率的两个垂直p-n结的多结微盘调制器，以实现高速调制和低功耗。