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1.发明申请METHOD OF OPERATING TRANSISTORS AND STRUCTURES THEREOF FOR IMPROVED RELIABILITY AND LIFETIME 有权用于改善可靠性和寿命的晶体管及其结构的操作方法公开(公告)号：US20100182729A1
公开(公告)日：2010-07-22
申请号：US12355815
申请日：2009-01-19
CPC分类号： H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.
摘要翻译： 本发明的实施例提供一种半导体器件，其包括具有第一，第二和第三节点的晶体管器件; 以及具有至少一根导线的互连结构，并且所述导线具有第一和第二端，所述导线的第一端连接到晶体管器件的第一，第二和第三节点之一。 导线是导电的并且适于在正常操作模式期间在第一方向上提供工作电流，并且适于在半导体器件的修复模式期间在与第一方向相反的第二方向上提供修复电流。 在一个实施例中，晶体管器件是双极晶体管，其中第一，第二和第三节点是双极晶体管的发射极，基极和集电极。 导线连接到发射极和集电极之一。 还公开了用于半导体器件的半导体器件和电流供应电路的操作方法。
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2.发明授权Method of operating transistors and structures thereof for improved reliability and lifetime 有权操作晶体管及其结构的方法，以提高可靠性和寿命公开(公告)号：US08159814B2
公开(公告)日：2012-04-17
申请号：US12355815
申请日：2009-01-19
CPC分类号： H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the present invention provide a semiconductor device that includes a transistor device having a first, a second, and a third node; and an interconnect structure having at least one wire and the wire having a first and a second end with the first end of the wire being connected to one of the first, the second, and the third node of the transistor device. The wire is conductive and adapted to provide an operating current in a first direction during a normal operating mode, and adapted to provide a repairing current in a second direction opposite to the first direction during a repair mode of the semiconductor device. In one embodiment the transistor device is a bipolar transistor with the first, second, and third nodes being an emitter, a base, and a collector of the bipolar transistor. The wire is connected to one of the emitter and the collector. Method of operating the semiconductor device and current supplying circuit for the semiconductor device are also disclosed.
摘要翻译： 本发明的实施例提供一种半导体器件，其包括具有第一，第二和第三节点的晶体管器件; 以及具有至少一根导线的互连结构，并且所述导线具有第一和第二端，所述导线的第一端连接到晶体管器件的第一，第二和第三节点之一。 导线是导电的并且适于在正常操作模式期间在第一方向上提供工作电流，并且适于在半导体器件的修复模式期间在与第一方向相反的第二方向上提供修复电流。 在一个实施例中，晶体管器件是双极晶体管，其中第一，第二和第三节点是双极晶体管的发射极，基极和集电极。 导线连接到发射极和集电极之一。 还公开了用于半导体器件的半导体器件和电流供应电路的操作方法。
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公开(公告)号：US08853693B2
公开(公告)日：2014-10-07
申请号：US13423823
申请日：2012-03-19
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01L21/00 , H01L21/768 , H01L21/66
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.
摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。
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公开(公告)号：US20110073858A1
公开(公告)日：2011-03-31
申请号：US12566726
申请日：2009-09-25
申请人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
发明人： Hanyi Ding , Kai D. Feng , Ping-Chuan Wang , Zhijian Yang
CPC分类号： H01L22/34 , H01L21/76898
摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.
摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。 确定半导体芯片中的硅通孔（TSV）的深度的方法包括将第一TSV蚀刻到半导体芯片中; 形成第一通道，所述第一通道包括第一TSV，电连接到第一TSV的第一触点和第二触点; 将电流源连接到第二触点; 确定跨越第一通道的电阻; 以及基于所述第一通道的电阻确定所述第一TSV的深度。
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5.发明授权Methodology and apparatus for tuning driving current of semiconductor transistors 有权用于调谐半导体晶体管的驱动电流的方法和装置公开(公告)号：US08779838B2
公开(公告)日：2014-07-15
申请号：US13280666
申请日：2011-10-25
IPC分类号： H03K17/687
CPC分类号： H01L29/66477 , G01R31/275 , H01L21/326 , H01L29/7833
摘要： A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.
摘要翻译： 用于修复晶体管的方法和装置包括向源极施加第一电压，向栅极施加第二电压并将第三电压施加到漏极达预定时间。以这种方式，半导体结构可以被修复或返回到位于或靠近 原有经营特点。
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公开(公告)号：US08525549B1
公开(公告)日：2013-09-03
申请号：US13403339
申请日：2012-02-23
申请人： Kai D. Feng , Hailing Wang , Ping-Chuan Wang , Zhijian Yang
发明人： Kai D. Feng , Hailing Wang , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H03K19/173
CPC分类号： H03K5/156 , H03K5/1534
摘要： A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.
摘要翻译： 一种功能单元，包括第一场效应晶体管（FET）器件，第二FET器件，连接到第一FET器件的栅极端子的第一节点和第二FET器件的栅极端子，其中第一节点可操作以接收 来自交流（AC）电压源的电压信号，连接到第一FET器件和第二FET器件的放大器部分，用于接收来自第一FET器件和第二FET器件的信号的放大器部分，相位比较器 部分具有连接到放大器的输出端子的第一输入端子和用于从AC电压源接收电压信号的第二输入端子，该相位比较器部分用于输出指示二进制值的位的电压。
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7.发明申请METHODOLOGY AND APPARATUS FOR TUNING DRIVING CURRENT OF SEMICONDUCTOR TRANSISTORS 有权用于调谐半导体晶体管驱动电流的方法和装置公开(公告)号：US20130099853A1
公开(公告)日：2013-04-25
申请号：US13280666
申请日：2011-10-25
CPC分类号： H01L29/66477 , G01R31/275 , H01L21/326 , H01L29/7833
摘要： A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.
摘要翻译： 用于修复晶体管的方法和装置包括向源极施加第一电压，向栅极施加第二电压并将第三电压施加到漏极达预定时间。以这种方式，半导体结构可以被修复或返回到位于或靠近 原有经营特点。
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公开(公告)号：US08274301B2
公开(公告)日：2012-09-25
申请号：US12610683
申请日：2009-11-02
CPC分类号： G01R31/2856 , G01R31/2875
摘要： An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.
摘要翻译： 嵌入在半导体芯片上的加速故障指示器包括绝缘区域; 位于绝缘区域内的电路; 位于所述绝缘区域内的加热元件，所述加热元件构造成将所述电路加热至高于所述半导体芯片的工作温度的温度; 以及可靠性监视器，其被配置为监视所述电路的劣化，并且还被配置为在所述电路的劣化超过预定阈值的情况下触发警报。 一种操作嵌入在半导体芯片上的加速故障指示器的方法包括确定半导体芯片的工作温度; 将位于加速故障指示器的绝缘区域内的电路加热到高于所确定的工作温度的温度; 监控电路退化; 并且在电路的劣化超过预定阈值的情况下触发报警。
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公开(公告)号：US20130233608A1
公开(公告)日：2013-09-12
申请号：US13414825
申请日：2012-03-08
申请人： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
发明人： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
CPC分类号： H01L23/5222 , H01L21/0274 , H01L21/3212 , H01L21/76816 , H01L21/76834 , H01L21/76837 , H01L21/7684 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H04L9/3278 , H04L2209/12 , H05K1/0289 , Y10T29/49117 , Y10T29/49165 , H01L2924/00
摘要： A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
摘要翻译： 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。
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10.发明授权公开(公告)号：US09331012B2
公开(公告)日：2016-05-03
申请号：US13414825
申请日：2012-03-08
申请人： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
发明人： Kai D. Feng , Wai-Kin Li , Ping-Chuan Wang , Zhijian Yang
IPC分类号： H01K3/10 , H01L23/522 , H01L23/528 , H04L9/32 , H05K1/02
CPC分类号： H01L23/5222 , H01L21/0274 , H01L21/3212 , H01L21/76816 , H01L21/76834 , H01L21/76837 , H01L21/7684 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H04L9/3278 , H04L2209/12 , H05K1/0289 , Y10T29/49117 , Y10T29/49165 , H01L2924/00
摘要： A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.
摘要翻译： 一种用于制造互连功能阵列的方法包括在衬底上形成第一多条导线，在第一多条导线和衬底之上形成绝缘体层，去除绝缘体层的部分以限定暴露在绝缘体层中的空腔 衬底和第一多个导电线的部分，其中去除绝缘体层的部分导致暴露衬底和第一多个导电线的部分的空腔的基本上随机的排列，在腔中沉积导电材料 并且在所述空腔和所述绝缘体层中的所述导电材料的部分上形成第二多个导电线。
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