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    Poly opening polish process
    2.
    发明授权
    Poly opening polish process 有权
    多开口抛光工艺

    公开(公告)号：US08513128B2

    公开(公告)日：2013-08-20

    申请号：US13162776

    申请日：2011-06-17

    申请人： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    发明人： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    IPC分类号： H01L21/304 ,  H01L21/306 ,  B44C1/22

    CPC分类号： H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

    摘要： A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

    摘要翻译： 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

    SEMICONDUCTOR PROCESS
    3.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20130052825A1

    公开(公告)日：2013-02-28

    申请号：US13220692

    申请日：2011-08-30

    申请人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    发明人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    IPC分类号： H01L21/306

    CPC分类号： H01L21/3212 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/7684 ,  H01L21/823835 ,  H01L29/665

    摘要： A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

    摘要翻译： 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。

    POLY OPENING POLISH PROCESS
    4.
    发明申请
    POLY OPENING POLISH PROCESS 有权

    公开(公告)号：US20120322265A1

    公开(公告)日：2012-12-20

    申请号：US13162776

    申请日：2011-06-17

    申请人： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    发明人： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

    IPC分类号： H01L21/304 ,  H01L21/306

    CPC分类号： H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

    摘要： A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

    摘要翻译： 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

    Semiconductor process
    8.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US08647986B2

    公开(公告)日：2014-02-11

    申请号：US13220692

    申请日：2011-08-30

    申请人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    发明人： Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chun-Wei Hsu ,  Yen-Ming Chen ,  Chih-Hsun Lin ,  Chang-Hung Kung

    IPC分类号： H01L21/306 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/768

    CPC分类号： H01L21/3212 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/7684 ,  H01L21/823835 ,  H01L29/665

    摘要： A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.

    摘要翻译： 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上，其中第一栅极结构的顶部包括盖层，使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面，或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。

    Semiconductor process
    9.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US08765588B2

    公开(公告)日：2014-07-01

    申请号：US13248011

    申请日：2011-09-28

    申请人： Pong-Wey Huang ,  Chan-Lon Yang ,  Chang-Hung Kung ,  Wei-Hsin Liu ,  Ya-Hsueh Hsieh ,  Bor-Shyang Liao ,  Teng-Chun Hsuan ,  Chun-Yao Yang

    发明人： Pong-Wey Huang ,  Chan-Lon Yang ,  Chang-Hung Kung ,  Wei-Hsin Liu ,  Ya-Hsueh Hsieh ,  Bor-Shyang Liao ,  Teng-Chun Hsuan ,  Chun-Yao Yang

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545

    摘要： A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.

    摘要翻译： 半导体工艺包括以下步骤。 介电层形成在基板上，并且介电层具有第一凹槽和第二凹槽。 形成金属层以覆盖介电层的表面，第一凹部和第二凹部。 部分地将牺牲的材料填充到第一凹部和第二凹部中，使得每个凹部中的金属层的一部分分别被覆盖。 去除每个凹部中的未覆盖的金属层。 牺牲的材料被去除。 执行蚀刻处理以去除第一凹部中的剩余金属层并且将剩余的金属层保留在第二凹部中。

    SEMICONDUCTOR PROCESS
    10.
    发明申请
    SEMICONDUCTOR PROCESS 有权
    半导体工艺

    公开(公告)号：US20130078792A1

    公开(公告)日：2013-03-28

    申请号：US13248011

    申请日：2011-09-28

    申请人： Pong-Wey Huang ,  Chan-Lon Yang ,  Chang-Hung Kung ,  Wei-Hsin Liu ,  Ya-Hsueh Hsieh ,  Bor-Shyang Liao ,  Teng-Chun Hsuan ,  Chun-Yao Yang

    发明人： Pong-Wey Huang ,  Chan-Lon Yang ,  Chang-Hung Kung ,  Wei-Hsin Liu ,  Ya-Hsueh Hsieh ,  Bor-Shyang Liao ,  Teng-Chun Hsuan ,  Chun-Yao Yang

    IPC分类号： H01L21/28

    CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545

    摘要： A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.

    摘要翻译： 半导体工艺包括以下步骤。 介电层形成在基板上，并且介电层具有第一凹槽和第二凹槽。 形成金属层以覆盖介电层的表面，第一凹部和第二凹部。 部分地将牺牲的材料填充到第一凹部和第二凹部中，使得每个凹部中的金属层的一部分分别被覆盖。 去除每个凹部中的未覆盖的金属层。 牺牲的材料被去除。 执行蚀刻处理以去除第一凹部中的剩余金属层并且将剩余的金属层保留在第二凹部中。