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公开(公告)号:US08647986B2
公开(公告)日:2014-02-11
申请号:US13220692
申请日:2011-08-30
申请人: Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
发明人: Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
IPC分类号: H01L21/306 , H01L21/321 , H01L21/3105 , H01L21/768
CPC分类号: H01L21/3212 , H01L21/3105 , H01L21/31051 , H01L21/31053 , H01L21/7684 , H01L21/823835 , H01L29/665
摘要: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.
摘要翻译: 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上,其中第一栅极结构的顶部包括盖层,使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面,或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。
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公开(公告)号:US08779526B2
公开(公告)日:2014-07-15
申请号:US13283603
申请日:2011-10-28
申请人: Chun-Wei Hsu , Po-Cheng Huang , Ren-Peng Huang , Jie-Ning Yang , Chia-Lin Hsu , Teng-Chun Tsai , Chih-Hsun Lin , Chang-Hung Kung , Yen-Ming Chen , Yu-Ting Li
发明人: Chun-Wei Hsu , Po-Cheng Huang , Ren-Peng Huang , Jie-Ning Yang , Chia-Lin Hsu , Teng-Chun Tsai , Chih-Hsun Lin , Chang-Hung Kung , Yen-Ming Chen , Yu-Ting Li
IPC分类号: H01L29/78
CPC分类号: H01L27/0629
摘要: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.
摘要翻译: 公开了半导体器件的制造方法。 该方法包括以下步骤:提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底上形成浅沟槽隔离(STI); 在电阻区域的STI中形成槽; 并且在罐中形成电阻器,并且在与槽的两侧相邻的STI的表面上形成电阻器。
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公开(公告)号:US08513128B2
公开(公告)日:2013-08-20
申请号:US13162776
申请日:2011-06-17
申请人: Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Chang-Hung Kung , Chia-His Chen , Yen-Ming Chen
发明人: Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Chang-Hung Kung , Chia-His Chen , Yen-Ming Chen
IPC分类号: H01L21/304 , H01L21/306 , B44C1/22
CPC分类号: H01L21/31053 , H01L21/02065 , H01L29/517 , H01L29/66545
摘要: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.
摘要翻译: 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板,设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂,碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物,从而提高集成电路的性能,降低集成电路的生产成本。
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公开(公告)号:US20130052825A1
公开(公告)日:2013-02-28
申请号:US13220692
申请日:2011-08-30
申请人: Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
发明人: Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chun-Wei Hsu , Yen-Ming Chen , Chih-Hsun Lin , Chang-Hung Kung
IPC分类号: H01L21/306
CPC分类号: H01L21/3212 , H01L21/3105 , H01L21/31051 , H01L21/31053 , H01L21/7684 , H01L21/823835 , H01L29/665
摘要: A semiconductor process includes the following steps. A first gate structure and a second gate structure are formed on a substrate, wherein the top of the first gate structure includes a cap layer, so that the vertical height of the first gate structure is higher than the vertical height of the second gate structure. An interdielectric layer is formed on the substrate. A first chemical mechanical polishing process is performed to expose the top surface of the cap layer. A second chemical mechanical polishing process is performed to expose the top surface of the second gate structure or an etching process is performed to remove the interdielectric layer located on the second gate structure. A second chemical mechanical polishing process is then performed to remove the cap layer.
摘要翻译: 半导体工艺包括以下步骤。 第一栅极结构和第二栅极结构形成在基板上,其中第一栅极结构的顶部包括盖层,使得第一栅极结构的垂直高度高于第二栅极结构的垂直高度。 在基板上形成介电层。 执行第一化学机械抛光工艺以暴露盖层的顶表面。 执行第二化学机械抛光工艺以暴露第二栅极结构的顶表面,或执行蚀刻工艺以去除位于第二栅极结构上的介电层。 然后执行第二化学机械抛光工艺以除去盖层。
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5.
公开(公告)号:US08643069B2
公开(公告)日:2014-02-04
申请号:US13180556
申请日:2011-07-12
申请人: Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
发明人: Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
CPC分类号: H01L21/28008 , H01L21/28123 , H01L21/31053 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
摘要翻译: 具有金属栅极的半导体器件包括具有形成在其中的至少一个金属栅极的多个浅沟槽隔离物(STI)的基板,以及分别位于金属的两侧的至少一对辅助虚设结构 门和衬底上。
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公开(公告)号:US20130105912A1
公开(公告)日:2013-05-02
申请号:US13283603
申请日:2011-10-28
申请人: Chun-Wei Hsu , Po-Cheng Huang , Ren-Peng Huang , Jie-Ning Yang , Chia-Lin Hsu , Teng-Chun Tsai , Chih-Hsun Lin , Chang-Hung Kung , Yen-Ming Chen , Yu-Ting Li
发明人: Chun-Wei Hsu , Po-Cheng Huang , Ren-Peng Huang , Jie-Ning Yang , Chia-Lin Hsu , Teng-Chun Tsai , Chih-Hsun Lin , Chang-Hung Kung , Yen-Ming Chen , Yu-Ting Li
IPC分类号: H01L27/06 , H01L21/8234
CPC分类号: H01L27/0629
摘要: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.
摘要翻译: 公开了半导体器件的制造方法。 该方法包括以下步骤:提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底上形成浅沟槽隔离(STI); 在电阻区域的STI中形成槽; 并且在罐中形成电阻器,并且在与槽的两侧相邻的STI的表面上形成电阻器。
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7.
公开(公告)号:US20130015524A1
公开(公告)日:2013-01-17
申请号:US13180556
申请日:2011-07-12
申请人: Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
发明人: Chun-Wei Hsu , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Yen-Ming Chen , Chia-Hsi Chen , Chang-Hung Kung
CPC分类号: H01L21/28008 , H01L21/28123 , H01L21/31053 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要: A semiconductor device having a metal gate includes a substrate having a plurality of shallow trench isolations (STIs) formed therein, at least a metal gate positioned on the substrate, and at least a pair of auxiliary dummy structures respectively positioned at two sides of the metal gate and on the substrate.
摘要翻译: 具有金属栅极的半导体器件包括具有形成在其中的至少一个金属栅极的至少一个金属栅极和分别位于该金属的两侧的至少一对辅助虚拟结构的基板,其中形成有多个浅沟槽隔离物(STI) 门和衬底上。
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公开(公告)号:US20120322265A1
公开(公告)日:2012-12-20
申请号:US13162776
申请日:2011-06-17
申请人: Chun-Wei HSU , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Chang-Hung Kung , Chia-His Chen , Yen-Ming Chen
发明人: Chun-Wei HSU , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Chang-Hung Kung , Chia-His Chen , Yen-Ming Chen
IPC分类号: H01L21/304 , H01L21/306
CPC分类号: H01L21/31053 , H01L21/02065 , H01L29/517 , H01L29/66545
摘要: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.
摘要翻译: 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板,设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂,碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物,从而提高集成电路的性能,降低集成电路的生产成本。
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公开(公告)号:US20120264302A1
公开(公告)日:2012-10-18
申请号:US13085502
申请日:2011-04-13
申请人: Chun-Wei Hsu , Teng-Chun Tsai , Chia-Lin Hsu , Po-Cheng Huang , Chia-Hsi Chen , Yen-Ming Chen , Chih-Hsun Lin
发明人: Chun-Wei Hsu , Teng-Chun Tsai , Chia-Lin Hsu , Po-Cheng Huang , Chia-Hsi Chen , Yen-Ming Chen , Chih-Hsun Lin
IPC分类号: H01L21/306
CPC分类号: H01L21/31053 , H01L21/02065 , H01L21/76224 , H01L29/66545
摘要: A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.
摘要翻译: 化学机械抛光(CMP)工艺包括以下步骤:提供基材,用酸性浆料对基材进行第一抛光步骤,以及在第一抛光步骤之后用碱性浆料对基材进行第二抛光步骤。
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10.
公开(公告)号:US08552486B2
公开(公告)日:2013-10-08
申请号:US13007777
申请日:2011-01-17
申请人: Kun-Mao Wu , Chih-Hsun Lin , Yu-Lung Yeh , Kuan-Chi Tsai
发明人: Kun-Mao Wu , Chih-Hsun Lin , Yu-Lung Yeh , Kuan-Chi Tsai
IPC分类号: H01L27/108 , H01L29/94
CPC分类号: H01L27/10852 , H01L21/7687 , H01L23/5223 , H01L23/5227 , H01L23/5283 , H01L23/53295 , H01L28/10 , H01L28/40 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要: A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.
摘要翻译: 多个金属层包括顶部金属层。 在顶部金属层上设置超厚金属(UTM)层,其中在UTM层和顶部金属层之间不存在额外的金属层。 金属 - 绝缘体 - 金属(MIM)电容器设置在UTM层之下和顶部金属层之上。
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