摘要:
A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.
摘要:
A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译:高k栅极电介质和金属栅极结构的堆叠包括下部金属层,清除金属层和上部金属层。 清除金属层满足以下两个标准:1)反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属(M)2)具有更负的金属 每个氧原子吉布斯自由能用于形成氧化物,而不是下金属层的材料和上金属层的材料。 符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。 此外,清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。 结果,即使在CMOS积分期间的高温处理之后,总栅极电介质的等效氧化物厚度(EOT)减小,并且场效应晶体管保持恒定的阈值电压。
摘要:
A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.
摘要:
A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.
摘要:
A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译:高k栅极电介质和金属栅极结构的堆叠包括下部金属层,清除金属层和上部金属层。 清除金属层满足以下两个标准:1)反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属(M)2)具有更负的金属 每个氧原子吉布斯自由能用于形成氧化物,而不是下金属层的材料和上金属层的材料。 符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。 此外,清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。 结果,即使在CMOS积分期间的高温处理之后,总栅极电介质的等效氧化物厚度(EOT)减小,并且场效应晶体管保持恒定的阈值电压。
摘要:
A layered structure and semiconductor device and methods for fabricating a layered structure and semiconductor device. The layered structure includes: a base layer including a material containing titanium nitride, tantalum nitride, or a combination thereof; a conductive layer including a material containing: tantalum aluminum nitride, titanium aluminum nitride, tantalum silicon nitride, titanium silicon nitride, tantalum hafnium nitride, titanium hafnium nitride, hafnium nitride, hafnium carbide, tantalum carbide, vanadium nitride, niobium nitride, or any combination thereof; and a tungsten layer. The semiconductor device includes: a semiconductor substrate; a base layer; a conductive layer; and a tungsten layer.
摘要:
A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译:高k栅极电介质和金属栅极结构的堆叠包括下部金属层,清除金属层和上部金属层。 清除金属层满足以下两个标准:1)反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属(M)2)具有更负的金属 每个氧原子吉布斯自由能用于形成氧化物,而不是下金属层的材料和上金属层的材料。 符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。 此外,清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。 结果,即使在CMOS积分期间的高温处理之后,总栅极电介质的等效氧化物厚度(EOT)减小,并且场效应晶体管保持恒定的阈值电压。
摘要:
A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译:高k栅极电介质和金属栅极结构的堆叠包括下部金属层,清除金属层和上部金属层。 清除金属层满足以下两个标准:1)反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属(M)2)具有更负的金属 每个氧原子吉布斯自由能用于形成氧化物,而不是下金属层的材料和上金属层的材料。 符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。 此外,清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。 结果,即使在CMOS积分期间的高温处理之后,总栅极电介质的等效氧化物厚度(EOT)减小,并且场效应晶体管保持恒定的阈值电压。
摘要:
Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”) . The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.
摘要:
Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.