-
公开(公告)号：US09647453B2
公开(公告)日：2017-05-09
申请号：US14158759
申请日：2014-01-17
CPC分类号： H02J1/00 , G11C5/147 , H02J2001/008 , Y10T307/391
摘要： According to one general aspect, an apparatus may include a first power supply configured to generate a first power signal having one of a plurality of voltages, and a second power supply configured to generate a second power signal that includes a voltage equal to or higher than a voltage of the first power signal. The apparatus may include a first electrical circuit configured to be powered by the first power supply. The apparatus may also include a power mode controller configured to: determine the voltage of the first power signal during the next power state, and generate a selector control signal based upon the voltage of the first power signal. The apparatus may also include a power supply selector configured to dynamically electrically couple a second electrical circuit with either the first power signal or the second power signal, based upon the selector control signal.
-
公开(公告)号：US09330751B2
公开(公告)日：2016-05-03
申请号：US14579840
申请日：2014-12-22
申请人： Shahnaz Nagle , Prashant Kenkare
发明人： Shahnaz Nagle , Prashant Kenkare
IPC分类号： G11C11/40 , G11C11/419 , G11C8/08
CPC分类号： G11C11/419 , G11C8/08
摘要： A wordline driver supply block supporting multiple operation modes of a memory of a microprocessor in a device for reducing power consumption thereof.
摘要翻译： 一种字线驱动器供应块，其支持用于减少其功耗的装置中的微处理器的存储器的多种操作模式。
-
公开(公告)号：US07864617B2
公开(公告)日：2011-01-04
申请号：US12388911
申请日：2009-02-19
申请人： Prashant Kenkare
发明人： Prashant Kenkare
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/147
摘要： A memory includes a selection circuit and a write assist circuit. The selection circuit has a first input, a second input coupled to a first power supply voltage terminal, an output coupled to a power supply terminal of each of a plurality of memory cells, and a control input for receiving a write assist control signal. The write assist circuit is coupled to the first input of the selection circuit for reducing a voltage at the power supply terminal of each of the plurality of memory cells during a write operation and in response to an asserted write assist enable signal. The write assist circuit comprises a P-channel transistor and a bias voltage generator. The P-channel transistor is for reducing the voltage at the power supply terminal of each of the plurality of memory cells during the write operation. The bias voltage generator is for providing a variable bias voltage to the P-channel transistor.
摘要翻译： 存储器包括选择电路和写辅助电路。 选择电路具有第一输入端，耦合到第一电源电压端子的第二输入端，耦合到多个存储单元中的每一个的电源端子的输出端和用于接收写辅助控制信号的控制输入端。 写入辅助电路耦合到选择电路的第一输入端，用于在写入操作期间减小多个存储单元中的每一个的电源端子处的电压，并且响应于断言的写入辅助使能信号。 写辅助电路包括P沟道晶体管和偏置电压发生器。 P沟道晶体管用于在写入操作期间降低多个存储单元中的每一个的电源端子处的电压。 偏置电压发生器用于向P沟道晶体管提供可变偏置电压。
-
4.发明申请公开(公告)号：US20070094480A1
公开(公告)日：2007-04-26
申请号：US11552817
申请日：2006-10-25
IPC分类号： G06F9/34
摘要： A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
摘要翻译： 一种方法包括将第一交易条目存储到第一软件可配置存储位置，将第二交易条目存储到第二软件可配置存储位置，确定由第一交易条目指示的第一交易已经发生，确定由第一交易条目指示的第二交易 第二交易条目已经在第一交易之后发生，并且响应于确定第一交易发生和第二交易发生，存储在第二交易之后的至少一个时钟周期期间捕获的至少一个交易属性。 第一和第二软件可配置存储位置可以位于跟踪缓冲器中，其中至少一个事务属性被存储到跟踪缓冲器并且覆盖第一和第二事务属性。 每个交易条目可以包括死循环字段，连续交易需求字段和最后输入字段。
-
公开(公告)号：US5369052A
公开(公告)日：1994-11-29
申请号：US161362
申请日：1993-12-06
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76213 , H01L21/32 , Y10S148/116 , Y10S438/981
摘要： Dual field oxide isolation (34 & 42) is formed by oxidizing through a portion (44) of a silicon nitride layer (30), through an exposed portion (43) of a remaining portion (18) of a masking layer (16), and through an exposed portion (42) of a buffer layer (28), all of which overlie isolation regions (22) of the silicon substrate (12). The different portions vary the diffusion rate of oxygen so that different field oxide thicknesses are created in a single field oxidation cycle. Therefore, integrated circuits having both low voltage densely packed devices and high voltage devices can be fabricated on the same circuit.
摘要翻译： 通过氧化氮化硅层（30）的一部分（44），通过掩模层（16）的剩余部分（18）的暴露部分（43）来形成双场氧化物隔离（34和42） 并且通过缓冲层（28）的暴露部分（42），它们都覆盖在硅衬底（12）的隔离区域（22）上。 不同的部分改变氧的扩散速率，使得在单场氧化循环中产生不同的场氧化物厚度。 因此，可以在同一电路上制造具有低压密集装置和高电压装置的集成电路。
-
6.发明授权Memory pipelining in an integrated circuit memory device using shared word lines 有权在使用共享字线的集成电路存储器件中的存储器流水线公开(公告)号：US07545702B2
公开(公告)日：2009-06-09
申请号：US11459170
申请日：2006-07-21
CPC分类号： G11C7/1039 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/6082 , G11C2207/2245 , Y02D10/13
摘要： A method for pipelining a memory in an integrated circuit includes providing a first clock phase and providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping. The method further includes providing a first memory array and providing a second memory array, wherein the second memory array shares a wordline with the first memory array. The method further includes using said wordline to select at least one row of the first memory array during the first clock phase. The method further includes using said wordline to select at least one row of the second memory array during the second clock phase.
摘要翻译： 用于在集成电路中流水线存储器的方法包括提供第一时钟相位和提供第二时钟相位，其中第一时钟相位和第二时钟相位至少部分地不重叠。 该方法还包括提供第一存储器阵列并提供第二存储器阵列，其中第二存储器阵列与第一存储器阵列共享字线。 该方法还包括在第一时钟阶段期间使用所述字线来选择第一存储器阵列的至少一行。 该方法还包括在第二时钟阶段期间使用所述字线来选择第二存储器阵列的至少一行。
-
公开(公告)号：US20050286327A1
公开(公告)日：2005-12-29
申请号：US10865274
申请日：2004-06-10
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C7/12 , G11C8/16
摘要： A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.
摘要翻译： 存储器件包括多对互补位线和多个锁存电路。 多对互补位线对中的每一对耦合到一列存储单元。 每个锁存电路具有耦合到数据线和第一输出和第二输出的输入，以提供取决于数据线的值的互补锁存值。 对于多个锁存器中的每个锁存器，第一输出耦合到一对多对的第一位线，使得在存储器件操作期间第一位线的值被第一输出连续地确定，并且第二输出是 耦合到该对的第二位线，使得在存储器件操作期间第二位线的值由第二输出连续地确定。
-
公开(公告)号：US20080022047A1
公开(公告)日：2008-01-24
申请号：US11865495
申请日：2007-10-01
IPC分类号： G06F12/00
CPC分类号： G11C11/412 , G11C15/00
摘要： Storage circuits (180-183 and 280-281) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100), shared complementary write bit lines (101, 102), separate read bit lines (103-106), a shared read word line (107), and separate write word lines (108-111) are used. In an alternate embodiment (e.g. circuit 200), shared complementary write bit lines (201, 202), a shared read bit line (203), separate read word lines (206-207), and separate write word lines (208-209) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file (17), a branch unit (15), an SRAM (19), other modules (20), a cache (18), a buffer (21), and/or a memory (14).
摘要翻译： 存储电路（180 - 183和280 - 281）可用于低功耗操作，同时允许快速读取访问。 在一个实施例中（例如电路100），共享互补写位线（101,102），分离读位线（103-106），共享读字线（107）和单独写字线（108-111） 用过的。 在另一实施例（例如电路200）中，共享互补写位线（201,202），共享读位线（203），分离读字线（206-207）和单独写字线（208-209） 被使用。 存储电路可以用于各种上下文中，例如寄存器文件（17），分支单元（15），SRAM（19），其他模块（20），高速缓存（18）， 缓冲器（21）和/或存储器（14）。
-
公开(公告)号：US20070280026A1
公开(公告)日：2007-12-06
申请号：US11435942
申请日：2006-05-17
申请人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russel , Shayan Zhang , Michael Snyder
发明人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russel , Shayan Zhang , Michael Snyder
IPC分类号： G11C5/14
摘要： A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.
摘要翻译： 公开了一种具有低电压存储器件的器件。 该设备包括具有第一存储器拓扑的第一存储器和具有第二存储器拓扑的第二存储器，其中两个存储器位于集成电路中。 第一存储器是相对高密度存储器件，能够存储相对于第二存储器的大量数据。 第二存储器是能够相对于可以访问第一存储器的电压的低电压访问的低电压存储器件。 因此，当集成电路处于低电压工作模式时，第二存储器可访问，这可以表示第一存储器或集成电路的其它部分的数据保持状态（睡眠状态）。 因此，该设备能够在正常或主动操作模式下将大量数据存储在高密度存储器中，并且还可以在低电压操作模式期间访问低电压存储器。
-
10.发明申请公开(公告)号：US20070236263A1
公开(公告)日：2007-10-11
申请号：US11279018
申请日：2006-04-07
IPC分类号： H03B1/00
CPC分类号： H03K3/356147 , H03K3/012 , H03K5/133
摘要： A contention-free keeper circuit including a keeper circuit having a first node and a second node, is provided. The contention-free keeper circuit may further include a delay element for providing time delay. The contention-free keeper circuit may further include a high-to-low contention element coupled between the first node and a first supply, and coupled to the delay element output. The contention-free keeper circuit may further include a low-to-high contention elimination element coupled between the first node and a second supply, and coupled to the delay element output, (i) wherein responsive to a low-to-high transition at the first node and the time delay, the low-to-high contention elimination element eliminates a low-to-high contention within the keeper circuit, and (ii) wherein responsive to a high-to-low signal transition at the first node and the time delay, the high-to-low contention elimination element eliminates a high-to-low contention within the keeper circuit.
摘要翻译： 提供了一种无争用的保持电路，包括具有第一节点和第二节点的保持电路。 无争用的保持电路还可以包括用于提供时间延迟的延迟元件。 无争用的保持器电路还可以包括耦合在第一节点和第一电源之间并耦合到延迟元件输出的高到低争用元件。 无争用的保持器电路还可以包括耦合在第一节点和第二电源之间并耦合到延迟元件输出的低到高竞争消除元件，（i）其中响应于 第一节点和时间延迟，低到高的竞争消除元件消除了保持器电路内的低到高竞争，以及（ii）响应于第一节点处的高到低的信号转换，以及 时间延迟，高到低的竞争消除元件消除了保持器电路内的高到低的竞争。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.018 秒)
