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    Continuous time common mode feedback circuit, system, and method
    1.
    发明申请
    Continuous time common mode feedback circuit, system, and method 有权
    连续时间共模反馈电路，系统和方法

    公开(公告)号：US20080068083A1

    公开(公告)日：2008-03-20

    申请号：US11900929

    申请日：2007-09-12

    申请人： Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Ashish Sharma

    发明人： Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Ashish Sharma

    IPC分类号： H03F3/45

    CPC分类号： H03F1/3211 ,  H03F3/45192 ,  H03F3/45659 ,  H03F2200/513 ,  H03F2203/45082 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

    摘要： Embodiments of the present invention provide a low voltage continuous time common mode feedback (CMFB) module, for low voltage operational amplifiers, providing good linearity, wide bandwidth and low systematic offset. The common mode feedback module includes a controlling module and an initializing module. The controlling module and the initializing module are parallel common mode feedback loops. The controlling module is a main CMFB loop and the initializing module is an auxiliary CMFB loop and both the loops work simultaneously. The controlling module and the initializing module receive a first differential input voltage and a second differential input voltage supplied by differential outputs of a main differential amplifier. Both the CMFB loops are low gain amplifiers in order to provide operation as linear as possible over the entire differential output operating range of the main differential amplifier.

    摘要翻译： 本发明的实施例为低电压运算放大器提供低电压连续时间共模反馈（CMFB）模块，提供良好的线性度，宽带宽和低系统偏移。 共模反馈模块包括控制模块和初始化模块。 控制模块和初始化模块是并联共模反馈回路。 控制模块是主CMFB循环，初始化模块是辅助CMFB循环，两个循环同时工作。 控制模块和初始化模块接收由主差分放大器的差分输出提供的第一差分输入电压和第二差分输入电压。 CMFB环路都是低增益放大器，以便在主差分放大器的整个差分输出工作范围内提供尽可能线性的操作。

    Continuous time common-mode feedback module and method with wide swing and good linearity
    2.
    发明申请
    Continuous time common-mode feedback module and method with wide swing and good linearity 有权
    连续时间共模反馈模块和方法具有宽摆幅和良好的线性度

    公开(公告)号：US20080074189A1

    公开(公告)日：2008-03-27

    申请号：US11900928

    申请日：2007-09-12

    申请人： Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik

    发明人： Pratap Singh ,  Chandrajit Debnath ,  Rakesh Malik

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45659 ,  H03F1/3211 ,  H03F3/45183 ,  H03F2203/45404 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45434 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

    摘要： A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.

    摘要翻译： 连续时间共模反馈模块能够在宽范围的输入电压下工作。 共模反馈模块包括共模检测器和用于计算和放大第一输入信号和第二输入信号的参考电压和共模电压的差的放大器。 共模反馈模块包括共模分解器和彼此耦合以提供共模反馈电压的控制电压产生模块。 共模反馈模块提供良好的线性度和宽带宽，无需补偿要求。 共模反馈模块还提供偏置电流和共模偏移的小过程角依赖性。

    Continuous time common-mode feedback module and method with wide swing and good linearity
    4.
    发明授权
    Continuous time common-mode feedback module and method with wide swing and good linearity 有权
    连续时间共模反馈模块和方法具有宽摆幅和良好的线性度

    公开(公告)号：US07671676B2

    公开(公告)日：2010-03-02

    申请号：US11900928

    申请日：2007-09-12

    申请人： Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik

    发明人： Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45659 ,  H03F1/3211 ,  H03F3/45183 ,  H03F2203/45404 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45434 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

    摘要： A continuous time common mode feedback module is capable of operating in a wide range of input voltages. The common mode feedback module includes a common mode detector and an amplifier for computing and amplifying the difference of a reference voltage and a common mode voltage of a first input signal and a second input signal. The common-mode feedback module includes a common mode resolver and a control voltage generating module coupled to each other to provide a common mode feedback voltage. The common mode feedback module provides a good linearity and a wide bandwidth, without compensation requirements. The common mode feedback module also provides small process corner dependence of bias current and a common mode offset.

    摘要翻译： 连续时间共模反馈模块能够在宽范围的输入电压下工作。 共模反馈模块包括共模检测器和用于计算和放大第一输入信号和第二输入信号的参考电压和共模电压的差的放大器。 共模反馈模块包括共模分解器和彼此耦合以提供共模反馈电压的控制电压产生模块。 共模反馈模块提供良好的线性度和宽带宽，无需补偿要求。 共模反馈模块还提供偏置电流和共模偏移的小过程角依赖性。

    Continuous time common mode feedback circuit, system, and method
    6.
    发明授权
    Continuous time common mode feedback circuit, system, and method 有权
    连续时间共模反馈电路，系统和方法

    公开(公告)号：US07652535B2

    公开(公告)日：2010-01-26

    申请号：US11900929

    申请日：2007-09-12

    申请人： Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Ashish Kumar Sharma

    发明人： Pratap N Singh ,  Chandrajit Debnath ,  Rakesh Malik ,  Ashish Kumar Sharma

    IPC分类号： H03F3/45

    CPC分类号： H03F1/3211 ,  H03F3/45192 ,  H03F3/45659 ,  H03F2200/513 ,  H03F2203/45082 ,  H03F2203/45424 ,  H03F2203/45428 ,  H03F2203/45521 ,  H03F2203/45642 ,  H03F2203/45681

    摘要： Embodiments of the present invention provide a low voltage continuous time common mode feedback (CMFB) module, for low voltage operational amplifiers, providing good linearity, wide bandwidth and low systematic offset. The common mode feedback module includes a controlling module and an initializing module. The controlling module and the initializing module are parallel common mode feedback loops. The controlling module is a main CMFB loop and the initializing module is an auxiliary CMFB loop and both the loops work simultaneously. The controlling module and the initializing module receive a first differential input voltage and a second differential input voltage supplied by differential outputs of a main differential amplifier. Both the CMFB loops are low gain amplifiers in order to provide operation as linear as possible over the entire differential output operating range of the main differential amplifier.

    摘要翻译： 本发明的实施例为低电压运算放大器提供低电压连续时间共模反馈（CMFB）模块，提供良好的线性度，宽带宽和低系统偏移。 共模反馈模块包括控制模块和初始化模块。 控制模块和初始化模块是并联共模反馈回路。 控制模块是主CMFB循环，初始化模块是辅助CMFB循环，两个循环同时工作。 控制模块和初始化模块接收由主差分放大器的差分输出提供的第一差分输入电压和第二差分输入电压。 CMFB环路都是低增益放大器，以便在主差分放大器的整个差分输出工作范围内提供尽可能线性的操作。

    Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT)
    7.
    发明申请
    Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT) 有权
    在SONET（同步光网络）虚级联（VCAT）中组合硬件和软件实现链路容量调整方案（LCAS）

    公开(公告)号：US20070047594A1

    公开(公告)日：2007-03-01

    申请号：US11210135

    申请日：2005-08-23

    申请人： Rakesh Malik ,  Dev Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

    发明人： Rakesh Malik ,  Dev Mukherjee ,  Harsh Chilwal ,  Dinesh Gupta

    IPC分类号： H04L12/56

    CPC分类号： H04J3/1611

    摘要： Combined hardware and software processing is applied in an end node of the network which includes mapping/demapping and deskewing. Most of the LCAS procedure is implemented in software so that it can be modified easily. Some of the procedure is implemented in hardware to meet stringent timing requirements. In particular, the handshaking protocol is implemented in software and the procedure for actually changing of the link capacity in response to the handshaking is implemented in hardware. The hardware and software communicate via a shared memory which includes a receive packet FIFO, receive control and status registers, a transmit packet FIFO, transmit control and status registers, and a transmit time slot interchange table.

    摘要翻译： 组合的硬件和软件处理应用于网络的终端节点，包括映射/解映射和去歪斜。 大多数LCAS程序都是以软件实现的，因此可以轻松修改。 一些程序在硬件中实现以满足严格的时序要求。 特别地，握手协议在软件中实现，并且响应于握手实际改变链路容量的过程在硬件中实现。 硬件和软件通过包括接收分组FIFO，接收控制和状态寄存器，发送分组FIFO，发送控制和状态寄存器以及发送时隙交换表的共享存储器进行通信。

    Device for implementing a sum of products expression
    8.
    发明申请
    Device for implementing a sum of products expression 有权
    用于实现产品表达式总和的设备

    公开(公告)号：US20060153321A1

    公开(公告)日：2006-07-13

    申请号：US11254935

    申请日：2005-10-20

    申请人： Aditya Bhuvanagiri ,  Rakesh Malik ,  Nitin Chawla

    发明人： Aditya Bhuvanagiri ,  Rakesh Malik ,  Nitin Chawla

    IPC分类号： H04B1/10

    CPC分类号： H03H17/0225

    摘要： A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.

    摘要翻译： 用于实现产品总和表达式的装置包括接收用于产生第一组部分优化的表达项的系数组/复合和乘积表达式的第一组2-输入移位和加法（2SAD）块 通过在其中应用递归优化，第二组1输入Shift-and-Add（1SAD）块从2SAD块接收响应，用于通过在其中应用垂直优化来产生第二组部分优化的表达项，第二组2SAD块 接收来自第一组2SAD块和第二组1SAD块的递归和垂直优化的响应，用于通过在其中应用水平优化来产生第三组部分优化的表达项，第二组2SAD块从块接收响应以产生 通过应用分解和因式分解的第四组部分优化表达式，以及从第四组接收响应的第五组2SAD块 的2SAD块，用于生成最终输出。

    Area efficient realization of coefficient architecture for bit-serial fir, IIR filters and combinational/sequential logic structure with zero latency clock output
    9.
    发明申请
    Area efficient realization of coefficient architecture for bit-serial fir, IIR filters and combinational/sequential logic structure with zero latency clock output 审中-公开
    区域有效实现位串行fir，IIR滤波器和具有零延迟时钟输出的组合/顺序逻辑结构的系数架构

    公开(公告)号：US20050193046A1

    公开(公告)日：2005-09-01

    申请号：US10968822

    申请日：2004-10-21

    申请人： Rakesh Malik ,  Puneet Goel

    发明人： Rakesh Malik ,  Puneet Goel

    IPC分类号： G06F17/10 ,  H03H17/02

    CPC分类号： H03H17/0225

    摘要： An area-efficient realization of a coefficient block [A] or architecture [A] with hardware sharing techniques and optimizations applied to this block. The block [A] is connected to coefficient lines coming from block [E] and/or [F], to be connected to perform filtering operation or a mathematical computing operation with optimization in hardware and to provide a zero latency output. Also provided is area minimal realization of digital filters based on coefficient block [A] when operated in bit serial fashion. The optimization techniques and structure applicable to linear digital filters typically a finite impulse response filter, infinite impulse response filter and for other filters and applications based on combinational logic consisting of a delay element, a multiplier, an adder and a subtractor.

    摘要翻译： 具有硬件共享技术和优化的系统块[A]或架构[A]的区域高效实现应用于该块。 块[A]连接到来自块[E]和/或[F]的系数线，以连接以执行滤波操作或以硬件优化的数学计算操作，并提供零延迟输出。 还提供了以比特串行方式操作时基于系数块[A]的数字滤波器的区域最小实现。 适用于线性数字滤波器的优化技术和结构通常是有限脉冲响应滤波器，无限脉冲响应滤波器，以及基于由延迟元件，乘法器，加法器和减法器组成的组合逻辑的其他滤波器和应用。

    Methods and apparatus for deskewing VCAT/LCAS members
    10.
    发明申请
    Methods and apparatus for deskewing VCAT/LCAS members 有权
    用于偏移VCAT / LCAS成员的方法和设备

    公开(公告)号：US20070047593A1

    公开(公告)日：2007-03-01

    申请号：US11210127

    申请日：2005-08-23

    申请人： Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Malik

    发明人： Dinesh Gupta ,  Dev Shankar Mukherjee ,  Rakesh Malik

    IPC分类号： H04J3/02

    CPC分类号： H04J3/0623 ,  H04J3/1611 ,  H04J2203/0094

    摘要： Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.

    摘要翻译： 写入逻辑和读取逻辑耦合到SDRAM和帧状态表。 VCG成员通过写逻辑写入SDRAM，帧状态表中的条目（基于MFI和SQ）由每个成员的写入逻辑维护。 读逻辑扫描帧状态表以识别SDRAM中数据可用的最早帧号。 基于帧状态和地址指针偏移，读逻辑维护每个VCG成员的状态表条目和每个VCG的状态。 根据优选实施例，读逻辑被提供在由临时缓冲器分开的两个部分中。 读逻辑的第一部分执行上述功能，并将块数据写入临时缓冲区。 读取逻辑的第二部分根据可选择的泄漏率从临时缓冲器读取字节数据。