Class-D amplifier with deadtime distortion compensation

    公开(公告)号:US11683015B2

    公开(公告)日:2023-06-20

    申请号:US17404862

    申请日:2021-08-17

    IPC分类号: H03F1/32 H03F3/217

    摘要: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

    Voltage-to-current architecture and error correction schemes

    公开(公告)号:US11536749B2

    公开(公告)日:2022-12-27

    申请号:US17154758

    申请日:2021-01-21

    摘要: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

    Dynamic common-mode adjustment for power amplifiers

    公开(公告)号:US12028030B2

    公开(公告)日:2024-07-02

    申请号:US17648958

    申请日:2022-01-26

    IPC分类号: H03F3/217 H03F3/45

    CPC分类号: H03F3/217 H03F2200/03

    摘要: Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.