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公开(公告)号：US11424672B2
公开(公告)日：2022-08-23
申请号：US17159082
申请日：2021-01-26
摘要： Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limit circuit comprising a first capacitive element, a charge circuit coupled to the first capacitive element, a first current source, a first resistive element coupled to the first current source, the capacitive element being coupled to a node between the resistive element and the first current source, a sample-and-hold circuit coupled to the first capacitive element, and a clamp circuit coupled between the sample-and-hold circuit and the feedback path.
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公开(公告)号：US11307604B2
公开(公告)日：2022-04-19
申请号：US17143382
申请日：2021-01-07
发明人： Kshitij Yadav , Sherif Galal
摘要： In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.
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公开(公告)号：US09473851B2
公开(公告)日：2016-10-18
申请号：US14579756
申请日：2014-12-22
发明人： Sherif Galal , Xinwang Zhang
CPC分类号： H04R3/007 , H03F1/523 , H03F3/185 , H03F3/2173 , H03F2200/03 , H03F2200/321 , H03F2200/462 , H03F2203/45138 , H03G3/20 , H03G3/3005 , H03G7/002 , H03G11/00 , H04R29/003
摘要： In one embodiment, a method for speaker operation comprises sensing an input common mode signal of a driver, wherein the driver drives a speaker, and adjusting the input common mode signal of the driver based on a difference between the sensed input common mode signal and a reference signal. The method also comprises sensing a current of a coil of the speaker, and control an output volume of the speaker based at least in part on the sensed current.
摘要翻译： 在一个实施例中，一种用于扬声器操作的方法包括感测驾驶员的输入共模信号，其中驱动器驱动扬声器，并且基于所感测的输入共模信号和 参考信号。 该方法还包括感测扬声器的线圈的电流，并且至少部分地基于所感测的电流来控制扬声器的输出音量。
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公开(公告)号：US11683015B2
公开(公告)日：2023-06-20
申请号：US17404862
申请日：2021-08-17
发明人： ChienChung Yang , Dongyang Tang , Sherif Galal , Xinwang Zhang , Subbarao Surendra Chakkirala , Pradeep Silva
CPC分类号： H03F1/3205 , H03F3/2173 , H03F2200/03 , H03F2200/165 , H03F2200/351
摘要： A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.
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公开(公告)号：US11536749B2
公开(公告)日：2022-12-27
申请号：US17154758
申请日：2021-01-21
发明人： Ramkumar Sivakumar , Jingxue Lu , Sherif Galal , Xinwang Zhang , Kshitij Yadav
摘要： Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
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公开(公告)号：US11374542B2
公开(公告)日：2022-06-28
申请号：US16799415
申请日：2020-02-24
摘要： Certain aspects of the present disclosure are generally directed to circuitry and techniques for current sensing. For example, certain aspects provide a circuit for signal amplification including a first amplifier, a second amplifier, and a third amplifier. The circuit also includes a first capacitive element coupled between a first output of the first amplifier and a first input of the third amplifier, a second capacitive element coupled between a second output of the first amplifier and a second input of the third amplifier, a third capacitive element coupled between a first output of the second amplifier and the first input of the third amplifier, and a fourth capacitive element coupled between a second output of the second amplifier and the second input of the third amplifier.
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公开(公告)号：US11885836B2
公开(公告)日：2024-01-30
申请号：US18146832
申请日：2022-12-27
发明人： Ramkumar Sivakumar , Jingxue Lu , Sherif Galal , Xinwang Zhang , Kshitij Yadav
CPC分类号： G01R19/0023 , H03F1/0227 , H03F3/2173 , H04R3/00 , H03F2200/03 , H03F2200/462 , H03F2200/481
摘要： Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
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公开(公告)号：US11133792B1
公开(公告)日：2021-09-28
申请号：US16885137
申请日：2020-05-27
发明人： Qubo Zhou , Sherif Galal
摘要： A level shifter includes a compact bias generator. The compact bias generator generates a first bias signal and a second bias signal, in the absence of a buffer. The level shifter also includes a first latch in a first stage to translate a first voltage to a second voltage based on the first bias signal. The level shifter further includes a second latch in a second stage to translate the first voltage to a third voltage based on the second bias signal. The first bias signal is independent of the second bias signal.
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公开(公告)号：US10944385B1
公开(公告)日：2021-03-09
申请号：US16894534
申请日：2020-06-05
摘要： In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.
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10.发明授权公开(公告)号：US10326405B2
公开(公告)日：2019-06-18
申请号：US15598389
申请日：2017-05-18
摘要： An amplifier circuit includes an amplifier and a voltage boost circuit configured to provide a variable supply voltage to the amplifier, the variable supply voltage continuously proportional to an audio input signal, the variable supply voltage configured to follow an output of the amplifier.
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