公开(公告)号：US20170277460A1

公开(公告)日：2017-09-28

申请号：US15081914

申请日：2016-03-27

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  DEXTER TAMIO CHUN ,  ALAIN ARTIERI

IPC: G06F3/06 ,  G11C11/406 ,  G11C7/10 ,  G06F12/08

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3275 ,  G06F12/0862 ,  G06F13/1689 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/602 ,  G11C11/40607 ,  G11C2211/4067 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

公开(公告)号：US20170116118A1

公开(公告)日：2017-04-27

申请号：US14921468

申请日：2015-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： ALAIN ARTIERI ,  SUBBARAO PALACHARLA ,  LAURENT MOLL ,  RAGHU SANKURATRI ,  Kedar Bhloe ,  Vinod Chamarty

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

Abstract: A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.