公开(公告)号：US09747038B2

公开(公告)日：2017-08-29

申请号：US14956728

申请日：2015-12-02

Applicant: QUALCOMM INCORPORATED

Inventor： Javid Jaffari ,  Amin Ansari ,  Rodolfo Beraha

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/0679 ,  G06F13/1684 ,  G06F13/1694 ,  G06F13/4234

Abstract: Systems and methods are disclosed for a hybrid parallel-serial memory access by a system on chip (SoC). The SoC is electrically coupled to the memory by both a parallel access channel and a separate serial access channel. A request for access to the memory is received. In response to receiving the request to access the memory, a type of memory access is identified. A determination is then made whether to access the memory with the serial access channel. In response to the determination to access the memory with the serial access channel, a first portion of the memory is accessed with the parallel access channel, and a second portion of the memory is accessed with the serial access channel.

公开(公告)号：US09685940B2

公开(公告)日：2017-06-20

申请号：US14818114

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Dorav Kumar ,  Steven James Dillen ,  Ohsang Kwon ,  Javid Jaffari

IPC: H03K17/04 ,  H03K17/042 ,  H03K5/24 ,  H03K19/00 ,  H03K5/26

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

公开(公告)号：US10296076B2

公开(公告)日：2019-05-21

申请号：US15156156

申请日：2016-05-16

Applicant: QUALCOMM Incorporated

Inventor： Javid Jaffari ,  Amin Ansari

IPC: G06F1/3296 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F1/3206 ,  G06F1/324

Abstract: Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.

公开(公告)号：US20170329391A1

公开(公告)日：2017-11-16

申请号：US15156156

申请日：2016-05-16

Applicant: QUALCOMM Incorporated

Inventor： Javid Jaffari ,  Amin Ansari

IPC: G06F1/32 ,  G06F1/28 ,  G06F1/08

CPC classification number: G06F1/3296 ,  G06F1/08 ,  G06F1/28 ,  G06F1/305 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: Supply voltage droop management circuits for reducing or avoiding supply voltage droops are disclosed. A supply voltage droop management circuit includes interrupt circuit configured to receive event signals generated by a functional circuit. Event signals correspond to an operational event that occurs in the functional circuit and increases load current demand to a power supply powering the functional circuit, causing supply voltage droop. The interrupt circuit is configured to generate an interrupt signal in response to the received event signal. Memory includes an operational event-frequency table having entries with a target frequency corresponding to an operational event. Operating the functional circuit at target frequency reduces the load current demand on the power supply, and supply voltage droop. A clock control circuit is configured to receive interrupt signal, access memory to determine the target frequency, and generate clock frequency adjustment signal to cause clock generator to adjust to the target frequency.

公开(公告)号：US09754923B1

公开(公告)日：2017-09-05

申请号：US15149646

申请日：2016-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jing Xie ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du ,  Javid Jaffari

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  G06F17/50 ,  H01L23/48 ,  H01L27/06

CPC classification number: H01L25/0657 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/78 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L24/13 ,  H01L25/16 ,  H01L27/0688 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1434

Abstract: Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.

公开(公告)号：US20160248414A1

公开(公告)日：2016-08-25

申请号：US14818114

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Dorav Kumar ,  Steven James Dillen ,  Ohsang Kwon ,  Javid Jaffari

IPC: H03K17/042 ,  H03K5/24

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

Abstract translation: 本文描述了为电路供电的系统和方法。 在一个实施例中，一种用于上电的方法包括将第一电源轨的电压与第二电源轨的电压进行比较，以及确定第一电源轨的电压是否在第二电源轨的电压的预定量内 至少基于该比较的预定时间段。 该方法还包括在确定第一电源轨的电压在第二电源轨的电压的预定量内至少在预定时间段内的情况下，启动耦合在第一和第二电源轨之间的多个开关的开关 时间。