Abstract:
An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.
Abstract:
A method and system for self-powering a clock input buffer is disclosed. The system includes an input node adapted to receive an alternating current (AC) signal having an instantaneous voltage oscillating between a minimum voltage and a maximum voltage. The system includes a pass transistor having a voltage controlled terminal, a first transfer terminal, and a second transfer terminal. The first transfer terminal connects to the input node and the second transfer terminal connects to a power node. The circuit also includes a plurality of transistors adapted to form a logic gate connected to the power node, and having a sensing terminal connected to the input node and an output terminal connected to the voltage controlled terminal. The logic gate produces a control voltage on the output terminal in response to an input voltage on the sensing terminal. The circuit also includes an energy-storage element having a first terminal connected to the power node.
Abstract:
A level-shifter is provided in which the devices may all be sized approximately the same yet a known startup state is provided at power-up by forming the level-shifter using a one-sided NMOS latch. The one-sided NMOS latch is powered through a pair of head-switch transistors. A pair of pull-down transistors function to flip a binary state for the one-sided NMOS latch.
Abstract:
An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.
Abstract:
An apparatus including: a current source configured to generate current; a bias node coupled to the current source; a switching current source circuit coupled to the current source and the bias node to allow the current to flow through the switching current source circuit into the bias node; a biasing circuit configured to receive a control signal from a phase detector, and mirror the current flowing through the switching current source circuit in response to the control signal; and a switch device disposed between the switching current source circuit and the biasing circuit to isolate the switching current source circuit from the biasing circuit.
Abstract:
An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.
Abstract:
An apparatus including: a current source configured to generate current; a bias node coupled to the current source; a switching current source circuit coupled to the current source and the bias node to allow the current to flow through the switching current source circuit into the bias node; a biasing circuit configured to receive a control signal from a phase detector, and mirror the current flowing through the switching current source circuit in response to the control signal; and a switch device disposed between the switching current source circuit and the biasing circuit to isolate the switching current source circuit from the biasing circuit.
Abstract:
An apparatus includes a phase detector coupled to an output of a frequency multiplier. A digital loop filter is coupled to the phase detector, and a duty cycle correction circuit is coupled to the digital loop filter.
Abstract:
A dual-band voltage controlled oscillator (VCO) includes: a first oscillator circuit including a first inductor; a second oscillator circuit including a second inductor; a first mode switch configured to electrically connect or disconnect a first output terminal of the first oscillator circuit and a first output terminal of the second oscillator circuit; a second mode switch configured to electrically connect or disconnect a second output terminal of the first oscillator circuit and a second output terminal of the second oscillator circuit; a third mode switch configured to electrically connect or disconnect a first terminal of the first inductor and a first terminal of the second inductor; and a fourth mode switch configured to electrically connect or disconnect a second terminal of the first inductor and a second terminal of the second inductor.
Abstract:
A circuit includes a digital-to-analog converter with non-uniform resolution for converting a digital signal into an analog signal. The digital-to-analog converter includes high-resolution circuitry, reduced-resolution circuitry coupled to the high-resolution circuitry and a switch coupled to the high-resolution circuitry and to the reduced-resolution circuitry. The switch couples one of the high-resolution circuitry and the reduced-resolution circuitry to an output node. The circuit also includes a decoder coupled to the switch. The decoder receives the digital signal to control the switch.