公开(公告)号：US20150279545A1

公开(公告)日：2015-10-01

申请号：US14229367

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Charles David Paynter ,  Ryan David Lane

IPC: H01F27/28 ,  H01F27/29 ,  H01F27/24

CPC classification number: H01F17/0013 ,  H01F2017/002 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011

Abstract: Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括芯层，第一通孔，第一介电层和第一电感器的封装衬底。 芯层包括第一表面和第二表面。 第一个通孔位于核心层。 第一介电层耦合到芯层的第一表面。 第一电感器位于第一电介质层中。 第一电感器耦合到芯层中的第一通孔。 第一电感器被配置为产生横向穿过封装衬底的磁场。 在一些实施方案中，封装衬底还包括耦合到第一电感器的第一焊盘，其中第一焊盘被配置为耦合到焊球。 在一些实施方案中，封装衬底包括位于芯层中的第二通孔和位于第一介电层中的第二电感器。

公开(公告)号：US09514966B2

公开(公告)日：2016-12-06

申请号：US14251236

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Charles David Paynter ,  Ryan David Lane

IPC: H01L23/58 ,  H01L21/48 ,  H01L23/552 ,  H01L23/66 ,  H01R13/6471

CPC classification number: H01L21/4885 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01R13/6471

Abstract: The disclosure is related to pin layouts in a semiconductor package. One embodiment of the disclosure provides a rhombus shaped shared reference pin layout that isolates a set of differential pin pairs. The differential signal pin pairs are configured such that an axis formed by a vertical signal pin pair is orthogonal to and mutually bisecting an axis formed by a lateral signal pin pair.

Abstract translation: 本公开涉及半导体封装中的引脚布局。 本公开的一个实施例提供了一种隔离一组差分引脚对的菱形共享参考引脚布局。 差分信号引脚对被配置为使得由垂直信号引脚对形成的轴线与横向信号引脚对形成的轴线正交并相互平分。

公开(公告)号：US10008316B2

公开(公告)日：2018-06-26

申请号：US14229367

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Charles David Paynter ,  Ryan David Lane

IPC: H01F5/00 ,  H01F27/28 ,  H01F17/00 ,  H01L23/498 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01F17/0013 ,  H01F2017/002 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011

Abstract: Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

公开(公告)号：US09536805B2

公开(公告)日：2017-01-03

申请号：US14324072

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Jiantao Zheng ,  Mario Francisco Velez ,  Sun Yun ,  Rajneesh Kumar ,  Houssam Wafic Jomaa

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/42 ,  H01L23/36 ,  H01L25/16 ,  H01L25/18 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L23/42 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/5385 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19106 ,  H01L2924/3511

Abstract: A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.

Abstract translation: 一种具有设置在基板上的处理器模块和设置在图案化盖上的辅助模块的混合封装。 辅助模块可以是与处理器模块一起位于包装中的存储器模块，电源管理集成电路（PMIC）模块和/或其他合适的模块。 将处理器模块的封装中的辅助模块降低处理器模块和基板之间的焊料凸块处的噪音。 将包含处理器模块的辅助模块也允许将其他模块添加到包装中，而不增加包装的面积。

公开(公告)号：US09214426B1

公开(公告)日：2015-12-15

申请号：US14329889

申请日：2014-07-11

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Priyatharshan Pathmanathan ,  John Stephen Loffink

IPC: H01L23/00 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/13 ,  H01L28/10 ,  H01L2224/02373 ,  H01L2224/13012 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1206 ,  H01L2924/19042 ,  H01L2924/00012 ,  H01L2924/014

Abstract: Methods and apparatuses for reducing excess on die capacitance. The method couples a first die pad to a first via. The method couples a second die pad to a second via. The method couples a first inductor to the first die pad and the second via. The method couples a second inductor to the second die pad and the first via.

Abstract translation: 减少裸片电容过剩的方法和装置。 该方法将第一管芯焊盘耦合到第一通孔。 该方法将第二管芯焊盘耦合到第二通孔。 该方法将第一电感器耦合到第一管芯焊盘和第二通孔。 该方法将第二电感器耦合到第二管芯焊盘和第一通孔。