公开(公告)号：US20170294422A1

公开(公告)日：2017-10-12

申请号：US15225910

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Michael James Solimando ,  William Stone ,  John Holmes ,  Christopher Healy ,  Rajendra Pendse ,  Sun Yun

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4882 ,  H01L21/54 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.

公开(公告)号：US10002857B2

公开(公告)日：2018-06-19

申请号：US15225910

申请日：2016-08-02

Applicant: QUALCOMM Incorporated

Inventor： Michael James Solimando ,  William Stone ,  John Holmes ,  Christopher Healy ,  Rajendra Pendse ,  Sun Yun

IPC: H01L23/367 ,  H01L23/02 ,  H01L25/065 ,  H01L21/54 ,  H01L25/10 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L21/4882 ,  H01L21/54 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/49827 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18162

Abstract: A package on package (PoP) device includes a first package, a thermal interface material, and a second package coupled to the first package. The first package includes a first integrated device and a first encapsulation layer that at least partially encapsulates the first integrated device, where the first encapsulation layer includes a first cavity located laterally with respect to the first integrated device. The thermal interface material (TIM) is coupled to the first integrated device such that the thermal interface material (TIM) is formed between the first integrated device and the second package. The thermal interface material (TIM) is formed in the first cavity of the first encapsulation layer.

公开(公告)号：US09460980B2

公开(公告)日：2016-10-04

申请号：US14625452

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Sun Yun ,  Rajneesh Kumar ,  Houssam Wafic Jomaa ,  Joan Rey V. Buot

IPC: H01L21/60 ,  H01L23/367 ,  H01L23/373 ,  H01L23/528 ,  H01L25/07

CPC classification number: H01L23/3675 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Some examples of the disclosure include a semiconductor package having a heat spreader, an outer perimeter portion attached to the bottom of the heat spreader along the perimeter and having a plurality of electrical pathways, a package substrate located below and spaced from the outer perimeter portion and having a plurality of electrical pathways, a plurality of connection points located between the outer perimeter component and the package substrate to provide connection points coupling the plurality of electrical pathways of the outer perimeter portion to the plurality of electrical pathways in the package substrate, and a cavity formed on the bottom of the heat spreader inside the outer perimeter portion.

Abstract translation: 本公开的一些示例包括具有散热器的半导体封装，沿着周边附接到散热器底部并具有多个电路径的外周边部分，位于外周部分下方并与外周部分隔开的封装基板， 具有多个电路径，多个连接点，位于所述外周边部件和所述封装衬底之间，以提供连接点，所述连接点将所述外周边部分的所述多个电通路连接到所述封装衬底中的所述多个电路径，以及 在外周部分内的散热器底部形成的空腔。

公开(公告)号：US09536805B2

公开(公告)日：2017-01-03

申请号：US14324072

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Jiantao Zheng ,  Mario Francisco Velez ,  Sun Yun ,  Rajneesh Kumar ,  Houssam Wafic Jomaa

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/42 ,  H01L23/36 ,  H01L25/16 ,  H01L25/18 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L23/42 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/5385 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19106 ,  H01L2924/3511

Abstract: A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.

Abstract translation: 一种具有设置在基板上的处理器模块和设置在图案化盖上的辅助模块的混合封装。 辅助模块可以是与处理器模块一起位于包装中的存储器模块，电源管理集成电路（PMIC）模块和/或其他合适的模块。 将处理器模块的封装中的辅助模块降低处理器模块和基板之间的焊料凸块处的噪音。 将包含处理器模块的辅助模块也允许将其他模块添加到包装中，而不增加包装的面积。