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33 条记录 (耗时 0.019 秒)

    EMBEDDED DIE PACKAGE ON PACKAGE (POP) WITH PRE-MOLDED LEADFRAME
    4.
    发明申请
    EMBEDDED DIE PACKAGE ON PACKAGE (POP) WITH PRE-MOLDED LEADFRAME 有权
    包装（POP）上嵌入的DIE包装与预先设计的铅笔

    公开(公告)号：US20090194887A1

    公开(公告)日：2009-08-06

    申请号：US12026742

    申请日：2008-02-06

    申请人： Yong Liu ,  Qiuxiao Qian

    发明人： Yong Liu ,  Qiuxiao Qian

    IPC分类号： H01L23/00 ,  H01L21/50

    CPC分类号： H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

    摘要翻译： 多芯片封装在将半导体管芯倒装芯片连接到引线框架之前形成顶部和底部预成型引线框架。 在芯片附接之后，使用底部填充物封装模具的除了一个表面之外的所有其它表面，并且顶部和底部引线框架通过焊料凸块球连接在一起，其中半导体芯片的暴露表面彼此靠近。

    Embedded semiconductor power modules and packages
    5.
    发明授权
    Embedded semiconductor power modules and packages 失效
    嵌入式半导体电源模块和封装

    公开(公告)号：US08421204B2

    公开(公告)日：2013-04-16

    申请号：US13110865

    申请日：2011-05-18

    申请人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu

    发明人： Yong Liu ,  Qiuxiao Qian ,  Yumin Liu

    IPC分类号： H01L23/52 ,  H01L21/00

    CPC分类号： H01L21/56 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/185 ,  H01L2924/00

    摘要： Disclosed are semiconductor die packages constructed from modules of embedded semiconductor dice and electrical components. In one embodiment, a semiconductor die package comprises a first module and a second module attached to the first module. One or more semiconductor dice are embedded in the first module, and one or more electrical components, such as surface-mounted components, are embedded in the second module. The first module may be formed by a lamination process, and the second module may be formed by a lamination process or a molding process. Patterned metal layers and vias provide electrical interconnections to the package and among the die and components of the package. The second module may be attached to the first module by coupling interconnect lands of separately manufactured modules to one another, or may be directly attached by lamination or molding.

    摘要翻译： 公开了由嵌入式半导体芯片和电气部件的模块构成的半导体管芯封装。 在一个实施例中，半导体管芯封装包括第一模块和连接到第一模块的第二模块。 一个或多个半导体裸片嵌入在第一模块中，并且一个或多个电组件，例如表面安装组件，嵌入在第二模块中。 第一模块可以通过层压工艺形成，并且第二模块可以通过层压工艺或模制工艺形成。 图案化的金属层和通孔提供对封装以及芯片和封装的部件之间的电互连。 第二模块可以通过将单独制造的模块的互连焊盘彼此连接，或者可以通过层压或模制来直接附接到第一模块。

    EMBEDDED DIE PACKAGE ON PACKAGE (POP) WITH PRE-MOLDED LEADFRAME
    7.
    发明申请
    EMBEDDED DIE PACKAGE ON PACKAGE (POP) WITH PRE-MOLDED LEADFRAME 有权
    包装（POP）上嵌入的DIE包装与预先设计的铅笔

    公开(公告)号：US20120094436A1

    公开(公告)日：2012-04-19

    申请号：US13276372

    申请日：2011-10-19

    申请人： Yong Liu ,  Qiuxiao Qian

    发明人： Yong Liu ,  Qiuxiao Qian

    IPC分类号： H01L21/60

    CPC分类号： H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A multiple-chip package has top and bottom pre-molded leadframes formed prior to the flip-chip attachment of semiconductor die to the leadframes. After die attachment, underfill is used to encase all but one surface of the die, and the top and bottom leadframes are joined together by solder bump balls with the exposed surfaces of the semiconductor dice proximate to each other.

    摘要翻译： 多芯片封装在将半导体管芯倒装芯片连接到引线框架之前形成顶部和底部预成型引线框架。 在芯片附接之后，使用底部填充物封装模具的除了一个表面之外的所有其它表面，并且顶部和底部引线框架通过焊料凸块球连接在一起，其中半导体芯片的暴露表面彼此靠近。

    WAFER LEVEL MOLDED OPTO-COUPLERS
    10.
    发明申请
    WAFER LEVEL MOLDED OPTO-COUPLERS 审中-公开
    WAFER LEVEL模制OPTO-COUPLERS

    公开(公告)号：US20120326170A1

    公开(公告)日：2012-12-27

    申请号：US13166697

    申请日：2011-06-22

    申请人： Yong Liu ,  Qiuxiao Qian

    发明人： Yong Liu ,  Qiuxiao Qian

    IPC分类号： H01L33/48 ,  H01L33/62

    CPC分类号： H01L25/167 ,  H01L21/568 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/00

    摘要： Optocoupler packages and methods of making the same. An exemplary package comprises a substrate having a first surface, a second surface opposite the first surface, and a body of electrically insulating material disposed between the first and second surfaces; a first optoelectronic device embedded in the body of electrically insulating material of the substrate and disposed between the substrate's first and second surfaces, the first optoelectronic device having a first conductive region and a second conductive region; a second optoelectronic device embedded in the body of electrically insulating material of the substrate and disposed between the substrate's first and second surfaces and optically coupled to the first optoelectronic device, the second optoelectronic device having a first conductive region and a second conductive region; and a plurality of electrical traces disposed on one or both surfaces of the substrate and electrically coupled to the conductive regions of the optoelectronic devices.

    摘要翻译： 光耦合器封装及其制作方法。 示例性包装包括具有第一表面，与第一表面相对的第二表面的基底和设置在第一和第二表面之间的电绝缘材料体; 第一光电子器件，其嵌入在所述衬底的电绝缘材料的主体中并且设置在所述衬底的第一和第二表面之间，所述第一光电器件具有第一导电区域和第二导电区域; 第二光电子器件，其嵌入在所述衬底的电绝缘材料的主体中并且设置在所述衬底的第一和第二表面之间并且光耦合到所述第一光电子器件，所述第二光电子器件具有第一导电区域和第二导电区域; 以及设置在所述基板的一个或两个表面上并电耦合到所述光电子器件的导电区域的多个电迹线。