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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20150243735A1

    公开(公告)日：2015-08-27

    申请号：US14711771

    申请日：2015-05-14

    Applicant: Renesas Electronics Corporation

    Inventor： Kazuo TOMITA ,  Toshiyuki OASHI ,  Hidenori SATO

    IPC: H01L29/06 ,  H01L29/45 ,  H01L23/528 ,  H01L27/092 ,  H01L29/10

    CPC classification number: H01L29/0696 ,  H01L21/823871 ,  H01L23/52 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/1095 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A gate interconnection portion (GHB) includes a first gate interconnection portion (GHB1), a second gate interconnection portion (GHB2), and a third gate interconnection portion (GHB3). The first gate interconnection portion (GHB1) is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region (PER). The second gate interconnection portion (GHB2) is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion (GHB1) toward the power supply interconnection, and extends across a boundary between the element formation region (PER) and an element isolation insulating film (EB), which is in parallel to an X axis direction. The third gate interconnection portion (GHB3) further extends in parallel to the Y-axis direction from the second gate interconnection portion (GHB2) toward the power supply interconnection.

    Abstract translation: 门互连部分（GHB）包括第一栅极互连部分（GHB1），第二栅极互连部分（GHB2）和第三栅极互连部分（GHB3）。 第一栅极互连部分（GHB1）平行于Y轴方向朝向电源互连形成，并延伸到元件形成区域（PER）内的规定位置。 第二栅极互连部（GHB2）与从第一栅极互连部（GHB1）朝向电源互连方向相对于Y轴方向倾斜地弯曲的方向平行地形成，并且跨越元件形成区域 （PER）和与X轴方向平行的元件隔离绝缘膜（EB）。 第三栅极互连部分（GHB3）还从第二栅极互连部分（GHB2）朝着电源互连方向平行于Y轴方向延伸。

    IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    成像装置及其制造方法

    公开(公告)号：US20150371958A1

    公开(公告)日：2015-12-24

    申请号：US14719462

    申请日：2015-05-22

    Applicant: Renesas Electronics Corporation

    Inventor： Kazuo TOMITA

    IPC: H01L23/00 ,  H01L27/146

    CPC classification number: H01L27/14632 ,  H01L23/585 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687

    Abstract: In an imaging device having a waveguide, a surface of an insulating film covering a seal ring is prevented from getting rough. A pixel region, a peripheral circuit region, and a seal region are defined over a semiconductor substrate. After formation of a pad electrode in the peripheral circuit region and a seal ring in the seal ring region, a TEOS film is so formed as to cover the pad electrode and the seal ring. A pattern of a photoresist for exposing a portion of the TEOS film covering the pad electrode and the seal ring, respectively, is formed and etching treatment is subjected to the exposed TEOS film. Then, after the pattern of the photoresist has been formed, a second waveguide holding hole is formed in the pixel region by performing etching treatment.

    Abstract translation: 在具有波导的成像装置中，防止覆盖密封环的绝缘膜的表面变粗糙。 像素区域，外围电路区域和密封区域被限定在半导体衬底上。 在外围电路区域中形成焊盘电极并且在密封环区域中形成密封环之后，形成TEOS膜以覆盖焊盘电极和密封环。 形成用于分别覆盖覆盖焊盘电极和密封环的TEOS膜的一部分的光致抗蚀剂的图案，并对暴露的TEOS膜进行蚀刻处理。 然后，在形成光致抗蚀剂的图案之后，通过进行蚀刻处理，在像素区域中形成第二波导保持孔。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150084164A1

    公开(公告)日：2015-03-26

    申请号：US14560985

    申请日：2014-12-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kazuo TOMITA

    IPC: H01L23/00 ,  H01L23/58 ,  H01L23/522

    CPC classification number: H01L23/585 ,  H01L21/78 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

    Abstract translation: 本公开提供了一种用于提高半导体器件的可靠性的技术，其中即使在具有用作层间绝缘膜的低k膜的半导体器件中，即使在切割到密封环时发生的裂纹扩展也可能受到限制。 在切割区域侧的每个层中形成虚拟过孔。 在俯视图中以矩阵形式，以相同的间隔形成虚拟通孔。 即使在切割时发生裂纹的情况下，也可以防止裂纹通过虚拟通孔扩散到密封环。 结果，可以提高在电路形成区域中吸收的水分的耐受性，并且可以防止可靠性的劣化。

    SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME 有权

    公开(公告)号：US20130040434A1

    公开(公告)日：2013-02-14

    申请号：US13646527

    申请日：2012-10-05

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kazuo TOMITA

    IPC: H01L21/336

    CPC classification number: H01L21/76229 ,  H01L21/31053 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200251429A1

    公开(公告)日：2020-08-06

    申请号：US16855705

    申请日：2020-04-22

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kazuo TOMITA

    IPC: H01L23/58 ,  H01L23/528 ,  H01L21/78 ,  H01L23/522 ,  H01L23/00

    Abstract: The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Vias are formed in each layer on a dicing region side. The vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

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