公开(公告)号：US12159934B2

公开(公告)日：2024-12-03

申请号：US17722788

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi Eikyu ,  Atsushi Sakai ,  Yotaro Goto

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

公开(公告)号：US12125905B2

公开(公告)日：2024-10-22

申请号：US16905071

申请日：2020-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinori Kaya ,  Katsumi Eikyu ,  Akihiro Shimomura ,  Hiroshi Yanagigawa ,  Kazuhisa Mori

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7828 ,  H01L29/7831 ,  H01L29/0692

Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

公开(公告)号：US11876127B2

公开(公告)日：2024-01-16

申请号：US17405648

申请日：2021-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro Imai ,  Yoshito Nakazawa ,  Katsumi Eikyu

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0607 ,  H01L29/66348

Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

公开(公告)号：US11830939B2

公开(公告)日：2023-11-28

申请号：US17405648

申请日：2021-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro Imai ,  Yoshito Nakazawa ,  Katsumi Eikyu

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L29/0607 ,  H01L29/66348

Abstract: An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

公开(公告)号：US11557648B2

公开(公告)日：2023-01-17

申请号：US17115204

申请日：2020-12-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi Yanagigawa ,  Katsumi Eikyu ,  Masami Sawada ,  Akihiro Shimomura ,  Kazuhisa Mori

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.

公开(公告)号：US10861786B2

公开(公告)日：2020-12-08

申请号：US16446078

申请日：2019-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshikazu Nagamura ,  Takashi Ipposhi ,  Katsumi Eikyu

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/532

Abstract: The semiconductor device has a wiring M 2, an interlayer insulating film IL3 formed on the wiring M 2, and two wirings M 3 formed on the interlayer insulating film IL3, and the wiring M 3 is connected to the wiring M 2 by a conductor layer PG2 formed in the interlayer insulating film IL3. A recess CC3 is formed on the upper surface IL3a of the interlayer insulating film IL3, and the recess CC3 is defined by a side surface S 31 connected to the upper surface IL3a and a side surface S 32 connected to the side surface S 31, and the side surface S 32 is inclined so that the width WC3 of the recess CC3 decreases in the direction from the upper surface IL3a of the interlayer insulating film IL3 toward the upper surface IL2a of the interlayer insulating film IL2.

公开(公告)号：US09437644B2

公开(公告)日：2016-09-06

申请号：US14528724

申请日：2014-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi Eikyu ,  Atsushi Sakai ,  Hiroyuki Arie

IPC: H01L27/146 ,  H01L31/028 ,  H01L31/18

CPC classification number: H01L27/14645 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1804

Abstract: To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.

Abstract translation: 为了提供具有高灵敏度的光电转换元件的半导体器件，引起较少的起霜，并且能够提供高可靠性的图像。 半导体器件具有半导体衬底，第一p型外延层，第二p型外延层和第一光电转换元件。 第一p型外延层形成在半导体衬底的主表面上。 形成第二p型外延层以覆盖第一p型外延层的上表面。 第一光电转换元件形成在第二p型外延层中。 第一和第二p型外延层各自由硅制成，并且第一p型外延层的p型杂质浓度高于第二p型外延层的p型杂质浓度。

公开(公告)号：US11646376B2

公开(公告)日：2023-05-09

申请号：US17480007

申请日：2021-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Eiji Tsukuda ,  Katsumi Eikyu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78391 ,  H01L29/42328 ,  H01L29/6684 ,  H01L29/66484 ,  H01L29/7831 ,  H01L29/6656

Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric film, a conductive film, at least one ferroelectric film, a second dielectric film, a memory gate electrode, a third dielectric film and a control gate electrode. The semiconductor substrate includes a source region and a drain region. The semiconductor substrate includes a first region and a second region between the source region and the drain region. The first dielectric film is formed on the first region. The conductive film is formed on the first dielectric film. The at least one ferroelectric film is formed on one hart of the conductive film. The second dielectric film is formed on the other part of the conductive film. The memory gate electrode is formed on the ferroelectric film. The third dielectric film is formed on the second region. The control gate electrode is formed on the third dielectric film.

公开(公告)号：US11527632B2

公开(公告)日：2022-12-13

申请号：US17316017

申请日：2021-05-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yotaro Goto ,  Katsumi Eikyu ,  Yoshihiro Nomura

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.

公开(公告)号：US11362207B2

公开(公告)日：2022-06-14

申请号：US17095241

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi Sakai ,  Satoru Tokuda ,  Ryuuji Umemoto ,  Katsumi Eikyu ,  Hiroshi Yanagigawa

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.