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公开(公告)号：US20170153838A1
公开(公告)日：2017-06-01
申请号：US15355322
申请日：2016-11-18
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Katsushige MATSUBARA , Seiji MOCHIZUKI , Ryoji HASHIMOTO , Toshiyuki KAYA , Kimihiko NAKAZAWA , Takahiro IRITA , Tetsuji TSUDA
CPC classification number: G06F3/0638 , G06F3/0604 , G06F3/0656 , G06F3/0673 , G06F7/544 , G06F2207/544 , H04N19/423
Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.
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公开(公告)号：US20200152248A1
公开(公告)日：2020-05-14
申请号：US16585858
申请日：2019-09-27
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tetsuji TSUDA , Yutaka FUNABASHI , Teruki FUKUYAMA
IPC: G11C7/22 , G11C11/4096 , G11C7/10
Abstract: An interference of control signals is caused by a deviation in the start timings of counting between counters of timer counter units of a first MCU and a second MCU. And thus, when a count value of the counter of the MCU of a parent reaches a predetermined value D, the MCU of the parent transmits a trigger signal to the MCU of a child. The MCU of the child obtains the time difference between the start timings of the counts of the counters of the parent and the child from the difference between the D and a count value E of the child at that time. A count period of the child until a maximum value of the count value is reached is adjusted by the time difference.
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公开(公告)号：US20170147252A1
公开(公告)日：2017-05-25
申请号：US15427207
申请日：2017-02-08
Applicant: Renesas Electronics Corporation
Inventor： Tetsuji TSUDA , Yoshiyuki ITO
IPC: G06F3/06
CPC classification number: G06F3/0631 , G06F3/0613 , G06F3/065 , G06F3/0659 , G06F3/0688 , G06F12/00 , G06F12/10 , G06F13/1668
Abstract: A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.
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公开(公告)号：US20190354646A1
公开(公告)日：2019-11-21
申请号：US16400872
申请日：2019-05-01
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tetsuji TSUDA , Teruki FUKUYAMA , Toshio SUNAMI
Abstract: A program is executed in an information processing device including a processor and a memory. The program allows the processor to execute a step of, on the basis of a simulation result of a model in the case where a series of blocks having an input block, one or more operation blocks, and an output block are allowed to operate at a predetermined clock frequency, deciding a new clock frequency of a target block that is allowed to operate at a clock frequency lower than the predetermined clock frequency, and a step of setting the conversion ratios of conversion blocks so as to execute a simulation of the model in which the target block is allowed to operate at the new clock frequency lower than the predetermined clock frequency and the remaining blocks are allowed to operate at the predetermined clock frequency.
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公开(公告)号：US20180349208A1
公开(公告)日：2018-12-06
申请号：US16100260
申请日：2018-08-10
Applicant: Renesas Electronics Corporation
Inventor： Tetsuji TSUDA , Masaru HASE , Yuki INOUE , Naohiro NISHIKAWA
CPC classification number: G06F9/52 , G06F9/4812
Abstract: A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a first register setting list and notifies the central processing unit of an access complete signal indicating completion of reading a second register setting list within a memory. The central processing unit changes the second register setting list within the memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the second register setting list changed by the central processing unit into the buffer to update the first register setting list based on the update request information.
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Patent Agency Ranking
公开(公告)号：US20180067675A1
公开(公告)日：2018-03-08
申请号：US15811828
申请日：2017-11-14
Applicant: Renesas Electronics Corporation
Inventor： Tetsuji TSUDA , Yoshiyuki ITO
CPC classification number: G06F3/0631 , G06F3/0613 , G06F3/065 , G06F3/0659 , G06F3/0688 , G06F12/00 , G06F12/10 , G06F13/1668
Abstract: A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.
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公开(公告)号：US20240094299A1
公开(公告)日：2024-03-21
申请号：US17934048
申请日：2022-09-21
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tetsuji TSUDA , Saika ARAI
IPC: G01R31/374 , G01R31/3835 , H01M10/42
CPC classification number: G01R31/374 , G01R31/3835 , H01M10/425 , H01M2220/20
Abstract: A battery simulator includes a circuit simulator that simulates an operation of an RC parallel circuit which is an equivalent circuit of a battery to be monitored and an RC parallel circuit optimization device that optimizes the RC parallel circuit based on a monitoring frequency of the battery, wherein the RC parallel circuit optimization device is configured to: delete a capacitance value of the RC parallel circuit when the monitoring frequency is determined to be a low frequency, and delete resistance and capacitance values of the RC parallel circuit when the monitoring frequency is determined to be a high frequency.
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公开(公告)号：US20180041357A1
公开(公告)日：2018-02-08
申请号：US15631284
申请日：2017-06-23
Applicant: Renesas Electronics Corporation
Inventor： Tetsuji TSUDA , Masaru HASE , Yuki INOUE , Katsushige MATSUBARA
CPC classification number: H04L12/2856 , G06F11/3034 , G11C5/04 , G11C29/025 , H01L2224/16 , H01L2924/1305
Abstract: A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.
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公开(公告)号：US20170161219A1
公开(公告)日：2017-06-08
申请号：US15357212
申请日：2016-11-21
Applicant: Renesas Electronics Corporation
Inventor： Masaru HASE , Tetsuji TSUDA , Naohiro NISHIKAWA , Yuki INOUE , Seiji MOCHIZUKI , Katsushige MATSUBARA , Ren IMAOKA
IPC: G06F13/362 , G06F13/40
CPC classification number: G06F13/362 , G06F13/4022 , G06F15/17312 , G06F15/7807
Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced.The semiconductor device includes a CPU section. and a. hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.
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公开(公告)号：US20170046069A1
公开(公告)日：2017-02-16
申请号：US15173634
申请日：2016-06-04
Applicant: Renesas Electronics Corporation
Inventor： Tetsuji TSUDA , Masaru Hase , Yuki Inoue , Naohiro Nishikawa
IPC: G06F3/06
CPC classification number: G06F9/52 , G06F9/4812
Abstract: A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a register setting list and notifies the central processing unit of an access complete signal indicating completion of reading the register setting list. The central processing unit changes the register setting list within a memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the register setting list changed by the central processing unit into the buffer based on the update request information.
Abstract translation: 半导体器件包括在一个半导体衬底上的中央处理单元和处理器。 处理器包括用于存储寄存器设置列表的缓冲器，并向中央处理单元通知指示完成读取寄存器设置列表的访问完成信号。 中央处理单元基于访问完成信号改变存储器内的寄存器设置列表，并向处理器通知更新请求信号。 处理器基于更新请求信息读取由中央处理单元改变为缓冲器的寄存器设置列表。
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