公开(公告)号：US20140080228A1

公开(公告)日：2014-03-20

申请号：US14022565

申请日：2013-09-10

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Naoya INOUE ,  Yoshihiro HAYASHI

IPC: H01L43/12

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

Abstract translation: 一种半导体器件，其中MRAM形成在包含在多层布线层中的布线层A中，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。

公开(公告)号：US20180069051A1

公开(公告)日：2018-03-08

申请号：US15697203

申请日：2017-09-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto UEKI ,  Takashi HASE

IPC: H01L27/24 ,  H01L27/10 ,  H01L43/12 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/101 ,  H01L27/2436 ,  H01L43/12 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1633

Abstract: A resistance change element includes first and second electrodes spaced apart from each other, a metal material layer adjacent to the first electrode, an oxide layer adjacent to each of the metal material layer and the first electrode, and a resistance change layer disposed continuously between the second and first electrodes and between the second electrode and the oxide layer. The resistance change layer is made of a metal oxide. The metal material layer is made of a metal or a metal compound. The oxide layer is made of an oxide of the material forming the metal material layer. The first electrode is made of ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, gold, or copper. A free energy of oxide formation of the oxide forming the oxide layer is higher than a free energy of oxide formation of the oxide forming the resistance change layer.

公开(公告)号：US20160365144A1

公开(公告)日：2016-12-15

申请号：US15099660

申请日：2016-04-15

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Koji MASUZAKI ,  Masaharu MATSUDAIRA ,  Takashi HASE ,  Yoshihiro HAYASHI

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79 ,  G11C2213/82

Abstract: Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.

Abstract translation: 包括各自包括电阻变化元件和控制电路的存储单元。 该电路执行On写入处理，以将存储单元中的On写入脉冲施加在电阻变化元件的电阻值低于第一基准值的电阻状态，以及用于 对具有第二参考值或更高的高电阻状态的ON写入脉冲施加具有相反极性的OFF写入脉冲。 该电路在On写入处理中应用与On写入脉冲具有相同极性的试用脉冲，其脉冲宽度短于On写入脉冲的脉冲宽度，并且具有与On 写入脉冲，按此顺序将“写入”脉冲应用于单元格。

公开(公告)号：US20170133434A1

公开(公告)日：2017-05-11

申请号：US15334846

申请日：2016-10-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto UEKI ,  Koji MASUZAKI ,  Takashi HASE ,  Yoshihiro HAYASHI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1625 ,  H01L45/1633

Abstract: A semiconductor device has a resistance change element that is high in the holding resistance of a low resistance (On) state while securing a memory window. In a resistance random access memory including selection transistors and resistance change elements coupled in series to the selection transistors, the resistance change element uses a lower electrode that applies a positive voltage when being transited to a high resistance (Off) state, an upper electrode that faces the lower electrode, and a resistance change layer that is sandwiched between the lower electrode and the upper electrode and that uses an oxide of transition metal. The resistance change layer contains nitrogen. The concentration of nitrogen on the lower electrode side is higher than that on the upper electrode side. The nitrogen in the resistance change layer exhibits a concentration gradient continuously declined from the lower electrode side to the upper electrode side.

公开(公告)号：US20160005792A1

公开(公告)日：2016-01-07

申请号：US14750060

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Nobuyuki IKARASHI ,  Jun KAWAHARA ,  Kiyoshi TAKEUCHI ,  Takashi HASE

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1658

Abstract: Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound Ta2O5 is produced and further Ru is diffused into the compound to form a layer (variable resistance layer) in which Ru is diffused into the compound Ta2O5. Such an incorporation of a metal (such as Ru) into a transition metal oxide TMO (such as Ta2O5) makes it possible to form electron conductive paths additional to filaments to lower the filaments in density and thickness. Thus, the memory element can be restrained from undergoing OFF-fixation, by which the element is not easily lowered in resistance, to be improved in ON-properties.

Abstract translation: 提供了一种改进了性能的半导体存储器件（电阻随机存取存储元件）。 通过溅射形成作为下电极的膜的Ru膜，并通过溅射在其上形成Ta膜。 接着，用等离子体氧化Ta膜，氧化Ta膜。 以这种方式，产生化合物Ta 2 O 5，并且进一步将Ru扩散到化合物中以形成其中Ru扩散到化合物Ta 2 O 5中的层（可变电阻层）。 金属（例如Ru）的这种引入到过渡金属氧化物TMO（例如Ta 2 O 5）中使得有可能形成除了长丝之外的电子传导路径以降低细丝的密度和厚度。 因此，可以抑制存储元件的导通性能的提高，使得元件不易于降低电阻的非固定。

公开(公告)号：US20150279923A1

公开(公告)日：2015-10-01

申请号：US14661043

申请日：2015-03-18

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Kiyoshi TAKEUCHI ,  Takashi HASE

IPC: H01L49/02 ,  H01L23/532 ,  H01L27/06 ,  H01L23/522

CPC classification number: H01L28/65 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/0629 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To provide a semiconductor device having less variation in characteristics. The semiconductor device is equipped with a plug formed in an interlayer insulating film, a lower electrode provided on the plug and to be coupled to the plug, a middle layer provided on the lower electrode and made of a metal oxide, and an upper electrode provided on the middle layer. The middle layer has a layered region contiguous to the lower electrode and the upper electrode. At least a portion of the layered region does not overlap with the plug. At least a portion of the plug does not overlap with the layered region.

Abstract translation: 提供具有较小的特性变化的半导体器件。 半导体器件配备有形成在层间绝缘膜中的插塞，设置在插塞上并与插头耦合的下电极，设置在下电极上并由金属氧化物制成的中间层，以及上电极 在中间层。 中间层具有与下部电极和上部电极邻接的分层区域。 层叠区域的至少一部分不与插头重叠。 塞子的至少一部分不与分层区域重叠。