公开(公告)号：US09786594B2

公开(公告)日：2017-10-10

申请号：US14516806

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shigeo Tokumitsu ,  Takahiro Mori ,  Tetsuya Nitta

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L23/532

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

公开(公告)号：US09691852B2

公开(公告)日：2017-06-27

申请号：US14704355

申请日：2015-05-05

Applicant: Renesas Electronics Corporation

Inventor： Shigeo Tokumitsu

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L27/092

CPC classification number: H01L21/76229 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

Abstract: An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

公开(公告)号：US11289363B2

公开(公告)日：2022-03-29

申请号：US16872766

申请日：2020-05-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shigeo Tokumitsu ,  Yoshiki Maruyama ,  Satoshi Iida

IPC: H01L21/74 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L21/306

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.

公开(公告)号：US10546802B2

公开(公告)日：2020-01-28

申请号：US15908597

申请日：2018-02-28

Applicant: Renesas Electronics Corporation

Inventor： Hiroaki Sekikawa ,  Shigeo Tokumitsu ,  Asuka Komuro

IPC: H01L23/48 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H01L23/522 ,  H01L27/092

Abstract: A substrate contact plug which is connected to a wiring and a semiconductor substrate and does not form a circuit is formed in a seal ring region in a peripheral portion of a semiconductor chip region. The substrate contact plug is buried in a trench which is deeper than an element isolation trench.

公开(公告)号：US10229909B2

公开(公告)日：2019-03-12

申请号：US15463681

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Shigeo Tokumitsu ,  Hiroki Fujii

IPC: H01L27/092 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10

Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.

公开(公告)号：US10074556B2

公开(公告)日：2018-09-11

申请号：US15180484

申请日：2016-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Shigeo Tokumitsu

IPC: H01L21/764 ,  H01L21/762 ,  H01L27/11526 ,  H01L21/311 ,  H01L21/308 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L27/11546 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L21/764 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.

公开(公告)号：US09881868B2

公开(公告)日：2018-01-30

申请号：US14516806

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shigeo Tokumitsu ,  Takahiro Mori ,  Tetsuya Nitta

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.