公开(公告)号：US09418996B2

公开(公告)日：2016-08-16

申请号：US15053551

申请日：2016-02-25

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract translation: 在高击穿电压MOSFET中使用STI绝缘膜导致由于漏极隔离绝缘膜的底角附近的冲击电离导致的可靠性降低。 本发明提供一种半导体集成电路器件的制造方法，其包括在其侧表面上形成硬掩模膜，其中的开口和侧壁绝缘膜; 在所述开口中形成浅沟槽，所述硬掩模膜作为掩模，并至少氧化暴露部分; 用绝缘膜填充沟槽，然后将其移除，使其离开开口中的沟槽，从而在沟槽内部和外部形成漏极偏移STI绝缘膜; 以及形成从栅极绝缘膜的上部延伸的栅极电极与其邻接的有源区域延伸到漏极绝缘膜的上部。

公开(公告)号：US20160005640A1

公开(公告)日：2016-01-07

申请号：US14738846

申请日：2015-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L21/762 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract translation: 在高击穿电压MOSFET中使用STI绝缘膜导致由于漏极隔离绝缘膜的底角附近的冲击电离导致的可靠性降低。 本发明提供一种半导体集成电路器件的制造方法，其包括在其侧表面上形成硬掩模膜，其中的开口和侧壁绝缘膜; 在所述开口中形成浅沟槽，所述硬掩模膜作为掩模，并至少氧化暴露部分; 用绝缘膜填充沟槽，然后将其移除，使其离开开口中的沟槽，从而在沟槽内部和外部形成漏极偏移STI绝缘膜; 以及形成从栅极绝缘膜的上部延伸的栅极电极与其邻接的有源区域延伸到漏极绝缘膜的上部。

公开(公告)号：US09960075B2

公开(公告)日：2018-05-01

申请号：US15497740

申请日：2017-04-26

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

公开(公告)号：US09305824B2

公开(公告)日：2016-04-05

申请号：US14738846

申请日：2015-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

公开(公告)号：US12293925B2

公开(公告)日：2025-05-06

申请号：US17894579

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki Murayama ,  Makoto Koshimizu ,  Takahiro Mori ,  Junjiro Sakai ,  Satoshi Iida

IPC: H01L21/4757 ,  H01L21/311 ,  H01L21/475 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

公开(公告)号：US11289363B2

公开(公告)日：2022-03-29

申请号：US16872766

申请日：2020-05-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shigeo Tokumitsu ,  Yoshiki Maruyama ,  Satoshi Iida

IPC: H01L21/74 ,  H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L21/306

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.

公开(公告)号：US09666584B2

公开(公告)日：2017-05-30

申请号：US15216856

申请日：2016-07-22

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.