公开(公告)号：US09859416B2

公开(公告)日：2018-01-02

申请号：US15172264

申请日：2016-06-03

Applicant: Renesas Electronics Corporation

Inventor： Takahiro Mori ,  Hiroki Fujii

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40

CPC classification number: H01L29/7823 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02255 ,  H01L21/311 ,  H01L29/0611 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/423 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835

Abstract: An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor.In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.

公开(公告)号：US20130249005A1

公开(公告)日：2013-09-26

申请号：US13902633

申请日：2013-05-24

Applicant: Renesas Electronics Corporation

Inventor： Hiroki Fujii

IPC: H01L27/06

CPC classification number: H01L27/0623 ,  H01L29/0692 ,  H01L29/8611 ,  H01L29/87

Abstract: A semiconductor device including a protection device and a protected device, the protection device includes a first semiconductor region of a second conductivity type formed over a substrate, a second semiconductor region of the second conductivity type provided in the first semiconductor region, having a higher impurity concentration than the first semiconductor region, a third semiconductor region of the second conductivity type formed in a surface layer of the second semiconductor region, having a higher impurity concentration than the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in the first semiconductor region and located away from the third semiconductor region, having a higher impurity concentration than the first semiconductor region, a fifth semiconductor region of a first conductivity type formed in the first semiconductor region and electrically short-circuited with the fourth semiconductor region, and a seventh semiconductor region of the first conductivity type.

Abstract translation: 一种包括保护装置和受保护装置的半导体装置，该保护装置包括形成在衬底上的第二导电类型的第一半导体区域，设置在第一半导体区域中的具有较高杂质的第二导电类型的第二半导体区域 浓度高于第一半导体区域，第二导电类型的第三半导体区域形成在具有比第二半导体区域更高的杂质浓度的第二半导体区域的表面层中，第二导电类型的第四半导体区域形成在第二半导体区域中， 第一半导体区域并且远离第三半导体区域，具有比第一半导体区域更高的杂质浓度，第一导电类型的第五半导体区域形成在第一半导体区域中并与第四半导体区域电短路，以及 第七个半导体 第一导电类型的ctor区域。

公开(公告)号：US10910492B2

公开(公告)日：2021-02-02

申请号：US16036489

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Hiroki Fujii ,  Atsushi Sakai ,  Takahiro Mori

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/732

Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.

公开(公告)号：US10468523B2

公开(公告)日：2019-11-05

申请号：US15847342

申请日：2017-12-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroki Fujii ,  Takahiro Mori

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762 ,  H01L29/423 ,  H01L21/3105 ,  H01L27/092 ,  H01L27/06 ,  H01L21/8238

Abstract: A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p+ source region and a p+ drain region. A p− drift region is located below the isolation trench and connected to the p+ drain region. A gate electrode fills the recessed portion. An n-type impurity region is located below the p− drift region and directly below the recessed portion.

公开(公告)号：US20160240664A1

公开(公告)日：2016-08-18

申请号：US15140888

申请日：2016-04-28

Applicant: Renesas Electronics Corporation

Inventor： Hiroki Fujii

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.

公开(公告)号：US20170365711A1

公开(公告)日：2017-12-21

申请号：US15693736

申请日：2017-09-01

Applicant: Renesas Electronics Corporation

Inventor： Hiroki Fujii

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.

公开(公告)号：US10217862B2

公开(公告)日：2019-02-26

申请号：US15837520

申请日：2017-12-11

Applicant: Renesas Electronics Corporation

Inventor： Takahiro Mori ,  Hiroki Fujii

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L29/10

Abstract: A semiconductor device including an isolation insulating film having a first thickness that is located between a drain region and a source region; a gate electrode formed over a region located between the isolation insulating film and the source region and that includes a part serving as a channel; an interlayer insulating film formed so as to cover the gate electrode; and a contact plug formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film, wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.

公开(公告)号：US09356138B2

公开(公告)日：2016-05-31

申请号：US14619194

申请日：2015-02-11

Applicant: Renesas Electronics Corporation

Inventor： Hiroki Fujii

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7825 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/7816 ,  H01L29/7835

Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.

Abstract translation: 提供了一种半导体器件，其具有嵌入在半导体衬底中的LDMOS晶体管，以提高源 - 漏击穿电压，具有防止由电场浓度引起的元件特性波动的设置，从而提高半导体器件的可靠性。 在每个LDMOS晶体管的分离绝缘膜的上表面上形成沟槽，沟槽具有部分地嵌入其中的栅电极。 这种结构防止了在分离绝缘膜的源极边缘附近的半导体衬底中的电场集中。

公开(公告)号：US09000565B2

公开(公告)日：2015-04-07

申请号：US13902633

申请日：2013-05-24

Applicant: Renesas Electronics Corporation

Inventor： Hiroki Fujii

IPC: H01L29/66 ,  H01L27/06 ,  H01L29/06 ,  H01L29/861 ,  H01L29/87

CPC classification number: H01L27/0623 ,  H01L29/0692 ,  H01L29/8611 ,  H01L29/87

Abstract: A semiconductor device including a protection device and a protected device, the protection device includes a first semiconductor region of a second conductivity type formed over a substrate, a second semiconductor region of the second conductivity type provided in the first semiconductor region, having a higher impurity concentration than the first semiconductor region, a third semiconductor region of the second conductivity type formed in a surface layer of the second semiconductor region, having a higher impurity concentration than the second semiconductor region, a fourth semiconductor region of the second conductivity type formed in the first semiconductor region and located away from the third semiconductor region, having a higher impurity concentration than the first semiconductor region, a fifth semiconductor region of a first conductivity type formed in the first semiconductor region and electrically short-circuited with the fourth semiconductor region, and a sixth semiconductor region of the first conductivity type.

Abstract translation: 一种包括保护装置和受保护装置的半导体装置，该保护装置包括形成在衬底上的第二导电类型的第一半导体区域，设置在第一半导体区域中的具有较高杂质的第二导电类型的第二半导体区域 浓度高于第一半导体区域，第二导电类型的第三半导体区域形成在具有比第二半导体区域更高的杂质浓度的第二半导体区域的表面层中，第二导电类型的第四半导体区域形成在第二半导体区域中， 第一半导体区域并且远离第三半导体区域，具有比第一半导体区域更高的杂质浓度，第一导电类型的第五半导体区域形成在第一半导体区域中并与第四半导体区域电短路，以及 第六半导体 或第一导电类型的区域。

公开(公告)号：US10229909B2

公开(公告)日：2019-03-12

申请号：US15463681

申请日：2017-03-20

Applicant: Renesas Electronics Corporation

Inventor： Shigeo Tokumitsu ,  Hiroki Fujii

IPC: H01L27/092 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10

Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.