公开(公告)号：US20160163654A1

公开(公告)日：2016-06-09

申请号：US14935481

申请日：2015-11-09

Applicant: Renesas Electronics Corporation

Inventor： Sho NAKANISHI

IPC: H01L23/552 ,  H01L29/739 ,  H01L27/06 ,  H01L29/868

CPC classification number: H01L29/7397 ,  H01L23/552 ,  H01L27/0664 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/868 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N+-type layer formed in the back surface of the semiconductor substrate, a back surface P+-type layer is formed in the back surface, and a surface P+-type layer is formed in the main surface right above the back surface P+-type layer to thereby promote the effect of hole injection from the back surface.

Abstract translation: 在背面空穴注入型二极管中，通过更有效地确保从半导体衬底的背面注入空穴的效果，提高了半导体器件的性能。 在半导体器件中，在由包括在半导体衬底的主表面中形成的阳极P型层和形成在半导体衬底的后表面中的背面N +型层的PN结构成的二极管中形成的背面 在后表面形成P +型层，并且在背面P +型层的正上方的主表面上形成表面P +型层，从而促进从后表面注入空穴的效果。

公开(公告)号：US20230387064A1

公开(公告)日：2023-11-30

申请号：US18188084

申请日：2023-03-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kodai OZAWA ,  Sho NAKANISHI

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/485

CPC classification number: H01L24/32 ,  H01L23/49513 ,  H01L23/485 ,  H01L2224/32245 ,  H01L2924/1815 ,  H01L2924/13055 ,  H01L2924/1203 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L29/0607

Abstract: A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.

公开(公告)号：US20170207331A1

公开(公告)日：2017-07-20

申请号：US15404509

申请日：2017-01-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sho NAKANISHI ,  Yuji FUJII

IPC: H01L29/739 ,  H01L29/66 ,  H01L27/06 ,  H01L23/535 ,  H01L29/08 ,  H01L29/36 ,  H01L21/265

CPC classification number: H01L29/7397 ,  H01L21/265 ,  H01L21/28518 ,  H01L23/535 ,  H01L27/0635 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/417 ,  H01L29/456 ,  H01L29/66348

Abstract: A performance of a semiconductor device including an RC-IGBT is improved. An AlNiSi layer (a layer containing aluminum (Al), nickel (Ni), and silicon (Si)) is formed between a back surface of a semiconductor substrate and a back surface electrode. Thus, a favorable ohmic junction can be obtained between the back surface electrode and an N+-type layer constituting a cathode region in an embedded diode, and a favorable ohmic junction can be obtained between the back surface electrode and a P-type layer constituting a collector region in an IGBT. The AlNiSi layer contains 10 at % or more of each of the aluminum (Al), the nickel (Ni), and the silicon (Si).

公开(公告)号：US20230268182A1

公开(公告)日：2023-08-24

申请号：US17993313

申请日：2022-11-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sho NAKANISHI ,  Kodai OZAWA

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L29/45 ,  H01L29/7813

Abstract: Disclosed is a technique for enhancing adhesion between a semiconductor substrate and a back surface electrode covering the back surface thereof. In particular, the enhancing adhesion technique includes: providing a semiconductor substrate SB having a main surface and a back surface opposite to the main surface, the back surface including n-type silicon; forming a first metal layer on the back surface of the semiconductor substrate SB, the first metal layer including nickel and vanadium which has a thermal diffusion coefficient smaller than that of nickel; performing a heat treatment to the semiconductor substrate to react silicon contained in the semiconductor substrate with nickel contained in the first metal layer to form a NiSiV layer in contact with the back surface of the semiconductor substrate; and forming a second metal including titanium on the NiSiV layer.

公开(公告)号：US20220140077A1

公开(公告)日：2022-05-05

申请号：US17516104

申请日：2021-11-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kodai OZAWA ,  Sho NAKANISHI

IPC: H01L29/08 ,  H01L29/861 ,  H01L29/739

Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.

公开(公告)号：US20170229551A1

公开(公告)日：2017-08-10

申请号：US15423283

申请日：2017-02-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Sho NAKANISHI

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L29/739 ,  H01L29/66

CPC classification number: H01L29/405 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41708 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/7809 ,  H01L29/7811 ,  H01L29/7813

Abstract: To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate resistive field plate is comprised of a first intermediate resistive field plate coupled, at one end thereof, to an inner-circumferential-side resistive field plate and, at the other end, to an outer-circumferential-side resistive field plate and a plurality of second intermediate resistive field plates. The first intermediate resistive field plate has a planar pattern that is equipped with a plurality of first portions separated from each other in a first direction connecting the inner-circumferential resistive field plate to the outer-circumferential-side resistive field plate and linearly extending in a second direction orthogonal to the first direction, and repeats reciprocation along the second direction. The second intermediate resistive field plates are each connected with a first end portion on one side of the first portions and extend with a curvature.

公开(公告)号：US20240290618A1

公开(公告)日：2024-08-29

申请号：US18437869

申请日：2024-02-09

Applicant: Renesas Electronics Corporation

Inventor： Yanzhe WANG ,  Sho NAKANISHI

IPC: H01L21/225 ,  H01L29/66

CPC classification number: H01L21/2254 ,  H01L29/6609

Abstract: A semiconductor substrate exposed from an oxidation-resistant mask layer is thermally oxidized to form a field oxidation film. The mask layer has multiple mask parts with a first width and multiple mask parts with a second width smaller than the first width. In the thermal oxidation process, an oxidation film is formed integrally with the field oxidation film under the mask part, and an oxidation film is formed integrally with the field oxidation film under the mask part. After removing the mask layer, plurality of p-type semiconductor regions is formed by ion-implantation into the semiconductor substrate using the field oxidation film as a mask. The plurality of p-type semiconductor regions includes a first semiconductor region formed under the oxidation film and a second semiconductor region formed under the oxidation film, and the depth of the second semiconductor region is shallower than the depth of the first semiconductor region.

公开(公告)号：US20240162305A1

公开(公告)日：2024-05-16

申请号：US18054996

申请日：2022-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kodai OZAWA ,  Sho NAKANISHI

IPC: H01L29/40 ,  H01L29/06

CPC classification number: H01L29/404 ,  H01L29/0623 ,  H01L29/401

Abstract: A manufacturing method of a semiconductor device includes: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) after the (a), forming an interlayer dielectric film on the upper surface of the semiconductor substrate; (c) after the (b), forming a base film on the interlayer dielectric film; (d) after the (c), forming a first conductive film on the base film; (e) after the (d), patterning the first conductive film to form a first wiring and a second wiring next to the first wiring; and (f) after the (e), removing the base film located between the first wiring and the second wiring. A material constituting the base film is different from a material constituting the first conductive film.

公开(公告)号：US20160359028A1

公开(公告)日：2016-12-08

申请号：US15239201

申请日：2016-08-17

Applicant: Renesas Electronics Corporation

Inventor： Sho NAKANISHI

IPC: H01L29/739 ,  H01L29/10 ,  H01L27/06 ,  H01L29/868 ,  H01L29/06

CPC classification number: H01L29/7397 ,  H01L23/552 ,  H01L27/0664 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/868 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the performance of a semiconductor device is improved. In the semiconductor device, in a diode formed of a P-N junction including an anode P-type layer formed in the main surface of a semiconductor substrate and a back surface N+-type layer formed in the back surface of the semiconductor substrate, a back surface P+-type layer is formed in the back surface, and a surface P+-type layer is formed in the main surface right above the back surface P+-type layer to thereby promote the effect of hole injection from the back surface.

公开(公告)号：US20240178277A1

公开(公告)日：2024-05-30

申请号：US18523734

申请日：2023-11-29

Applicant: Renesas Electronics Corporation

Inventor： Katsumi EIKYU ,  Ryota KURODA ,  Hitoshi MATSUURA ,  Sho NAKANISHI

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0804 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/41708 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor substrate includes a plurality of emitter formation regions separated from each other in a Y direction between a pair of trenches, and a separation region located between the emitter formation regions. A p-type base region is formed in the semiconductor substrate of each of the emitter formation regions and the separation region. An n-type impurity region is formed in the base region of each emitter formation region. The impurity region is also formed in the base region at a position in contact with the pair of trenches in the separation region.