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公开(公告)号:US20230116260A1
公开(公告)日:2023-04-13
申请号:US17892639
申请日:2022-08-22
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor: Nozomi ITO , Yorinobu KUNIMUNE , Kenichiro ABE , Nobuhito SHIRAISHI
IPC: H01C7/06 , H01C17/232 , H01C17/26 , H01L49/02
Abstract: A resistor material including a plurality of crystalline phases having a positive temperature coefficient of resistance, and an amorphous phase having a negative temperature coefficient of resistance and having a resistivity higher than the crystalline phase, in a mixed state, is provided. Moreover, a resistor element having a resistor film configured by the resistor material described above, and a method of manufacturing a resistor element by forming a film of an amorphous material having a negative temperature coefficient of resistance and subjecting this film to an annealing treatment to obtain the resistor element described above, are provided.
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公开(公告)号:US20140312406A1
公开(公告)日:2014-10-23
申请号:US14173074
申请日:2014-02-05
Applicant: Renesas Electronics Corporation
Inventor: Masao INOUE , Yoshiki MARUYAMA , Akio NISHIDA , Yorinobu KUNIMUNE , Kota FUNAYAMA
IPC: H01L29/49 , H01L29/423 , H01L21/28
CPC classification number: H01L29/4925 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02667 , H01L21/28035 , H01L21/28176 , H01L21/28273 , H01L29/42324 , H01L29/4916 , H01L29/66825
Abstract: To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film (21) on a substrate (10); forming an interlayer oxide layer (22) on a surface of the first polysilicon film (21); forming a second polysilicon film (23) in contact with the interlayer oxide layer (22) above the first polysilicon film (21); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film (23).
Abstract translation: 为了控制层叠多晶硅膜上的晶粒生长,提供了制造半导体器件的方法。 该方法包括:在衬底(10)上形成第一多晶硅膜(21); 在所述第一多晶硅膜(21)的表面上形成层间氧化物层(22); 形成与第一多晶硅膜(21)上方的层间氧化物层(22)接触的第二多晶硅膜(23)。 在形成第二多晶硅膜(23)之后,在含氮气体气氛中,在高于第一和第二多晶硅膜的成膜温度的温度下进行退火。
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公开(公告)号:US20250046705A1
公开(公告)日:2025-02-06
申请号:US18769072
申请日:2024-07-10
Applicant: Renesas Electronics Corporation
Inventor: Nobuhito SHIRAISHI , Yorinobu KUNIMUNE , Yoshimi KATO , Nozomi ITO , Mengnan YANG , Kenichiro SONODA
IPC: H01L23/522 , H01L21/02 , H01L21/768 , H01L23/532
Abstract: A semiconductor device includes a first dielectric film, a resistor element disposed on the first dielectric film, and a second dielectric film disposed on the resistor element. The resistor element contains silicon, chromium, and carbon. The silicon concentration in the resistor element increases from a center part of the resistor element towards an upper surface of the resistor element, and also increases from the center part of the resistor element towards a lower surface of the resistor element.
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