公开(公告)号：US20160071850A1

公开(公告)日：2016-03-10

申请号：US14931235

申请日：2015-11-03

Applicant: Renesas Electronics Corporation

Inventor： Misato SAKAMOTO ,  Yoshitake KATO ,  Youichi YAMAMOTO ,  Hitoshi KASAI ,  Satoshi ITOU

IPC: H01L27/108

CPC classification number: H01L27/10808 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/3212 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/60 ,  H01L28/87 ,  H01L28/91

Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.

Abstract translation: 电容元件具有改善的电性能。 电容元件配置在DRAM单元中，并且具有下电极，形成在下电极上的电容绝缘膜，以及形成在电容绝缘膜上的上电极。 上部电极具有从该电极的电容绝缘膜侧，第一上部电极，第二上部电极和第三上部电极依次层叠的结构。 第三上电极是可能含有杂质的钨膜。 在第一和第三上部电极之间，插入第二上部电极，其是用于防止第三上部电极中可能的杂质扩散到电容绝缘膜中的阻挡膜。

公开(公告)号：US20170047409A1

公开(公告)日：2017-02-16

申请号：US15306445

申请日：2014-05-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiro IIZUKA ,  Shin KOYAMA ,  Yoshitake KATO

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/205 ,  H01L29/778 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423

Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.

Abstract translation: 在半导体器件（MISFET）中，具有在栅极绝缘膜之间形成在氮化物半导体层上的栅电极，栅极绝缘膜包括形成在氮化物半导体层上的第一栅极绝缘膜（第一金属的氧化物膜）和 第二栅极绝缘膜（第二金属的氧化物膜）。 第二金属（例如，Hf）的电负性低于第一金属（例如，Al）的电负性。 由于第二金属的电负性低于第一金属的电负性，所以由于界面极化，负电荷被引入到第一金属的氧化物膜中，使得平带电压可以向正方向偏移。 因此，由于第一金属的氧化膜的热处理而变为负的阈值电压可以向正方向移动。

公开(公告)号：US20150270271A1

公开(公告)日：2015-09-24

申请号：US14661734

申请日：2015-03-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Misato SAKAMOTO ,  Yoshitake KATO ,  Youichi YAMAMOTO ,  Hitoshi KASAI ,  Satoshi ITOU

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/321 ,  H01L49/02 ,  H01L21/285

CPC classification number: H01L27/10808 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/3212 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/60 ,  H01L28/87 ,  H01L28/91

Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.

Abstract translation: 电容元件具有改善的电性能。 电容元件配置在DRAM单元中，并且具有下电极，形成在下电极上的电容绝缘膜，以及形成在电容绝缘膜上的上电极。 上部电极具有从该电极的电容绝缘膜侧，第一上部电极，第二上部电极和第三上部电极依次层叠的结构。 第三上电极是可能含有杂质的钨膜。 在第一和第三上部电极之间，插入第二上部电极，其是用于防止第三上部电极中可能的杂质扩散到电容绝缘膜中的阻挡膜。

公开(公告)号：US20170317183A1

公开(公告)日：2017-11-02

申请号：US15513545

申请日：2015-03-30

Applicant: Renesas Electronics Corporation

Inventor： Yoshitake KATO

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/40 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/7787

Abstract: The characteristics of a semiconductor device are enhanced. In a semiconductor device (MISFET) having a gate electrode GE formed on a nitride semiconductor layer CH via a gate insulating film GI, the gate insulating film GI is configured to have a first gate insulating film (oxide film of a first metal) GIa formed on the nitride semiconductor layer CH and a second gate insulating film (oxide film of a second metal) GIb. And, the second metal (e.g., Hf) has lower electronegativity than the first metal (e.g., Al). By thus making the electronegativity of the second metal lower than the electronegativity of the first metal, a threshold voltage (Vth) can be shifted in a positive direction. Moreover, the gate electrode GE is configured to have a first gate electrode (nitride film of a third metal) GEa formed on the second gate insulating film GIb and a second gate electrode (fourth metal) GEb. This prevents the diffusion of oxygen to the gate insulating film GI, and variations in the threshold voltage (Vth) can be reduced.