中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.011 seconds)

    Semiconductor Integrated Circuit Device and Method for Producing the Same
    1.
    发明申请
    Semiconductor Integrated Circuit Device and Method for Producing the Same 审中-公开
    半导体集成电路器件及其制造方法

    公开(公告)号：US20160071850A1

    公开(公告)日：2016-03-10

    申请号：US14931235

    申请日：2015-11-03

    Applicant: Renesas Electronics Corporation

    Inventor： Misato SAKAMOTO ,  Yoshitake KATO ,  Youichi YAMAMOTO ,  Hitoshi KASAI ,  Satoshi ITOU

    IPC: H01L27/108

    CPC classification number: H01L27/10808 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/3212 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/60 ,  H01L28/87 ,  H01L28/91

    Abstract: A capacitive element has improved electrical properties. The capacitive element is configured in a DRAM cell and has a lower electrode, a capacitive insulator film formed over the lower electrode, and an upper electrode formed over the capacitive insulator film. The upper electrode has a structure in which from the capacitive insulator film side of this electrode, a first upper electrode, a second upper electrode and a third upper electrode are stacked in turn. The third upper electrode is a tungsten film that may contain an impurity. Between the first and third upper electrodes, the second upper electrode is interposed which is a barrier film for preventing the possible impurity in the third upper electrode from diffusing into the capacitive insulator film.

    Abstract translation: 电容元件具有改善的电性能。 电容元件配置在DRAM单元中，并且具有下电极，形成在下电极上的电容绝缘膜，以及形成在电容绝缘膜上的上电极。 上部电极具有从该电极的电容绝缘膜侧，第一上部电极，第二上部电极和第三上部电极依次层叠的结构。 第三上电极是可能含有杂质的钨膜。 在第一和第三上部电极之间，插入第二上部电极，其是用于防止第三上部电极中可能的杂质扩散到电容绝缘膜中的阻挡膜。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的半导体器件和制造方法

    公开(公告)号：US20150372074A1

    公开(公告)日：2015-12-24

    申请号：US14836152

    申请日：2015-08-26

    Applicant: Renesas Electronics Corporation

    Inventor： Youichi YAMAMOTO ,  Naomi Fukumaki ,  Misato Sakamoto ,  Yoshitake Kato

    IPC: H01L49/02 ,  H01L27/108 ,  H01L21/31 ,  H01L21/285

    CPC classification number: H01L28/60 ,  H01L21/28088 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/31 ,  H01L21/76856 ,  H01L27/1085 ,  H01L28/91 ,  H01L29/517

    Abstract: A method for manufacturing a semiconductor device includes a capacitor element in which a capacitance dielectric film is provided between an upper electrode film and a lower electrode film, includes forming the lower electrode film over the semiconductor substrate, forming the capacitance dielectric film over the lower electrode film, and forming the upper electrode film over the capacitance dielectric film, wherein, an entire surface layer of the lower electrode film is formed of a polycrystalline titanium nitride. At the portion of the capacitance dielectric film where directly contacting the entire surface layer of the lower electrode is formed of a polycrystalline metal oxide, and the polycrystalline metal oxide is formed by an ALD method and inherits a crystallinity of the polycrystalline titanium nitride.

    Abstract translation: 一种制造半导体器件的方法，包括在上电极膜和下电极膜之间设置电容电介质膜的电容器元件，包括在半导体衬底上形成下电极膜，在下电极上形成电容电介质膜 膜，并且在电容电介质膜上形成上电极膜，其中，下电极膜的整个表面层由多晶氮化钛形成。 在直接接触下电极的整个表面层的电容电介质膜的部分由多晶金属氧化物形成，并且多晶金属氧化物通过ALD法形成并且继承了多晶氮化钛的结晶度。

Patent Agency Ranking