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    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    3.
    发明申请
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开

    公开(公告)号：US20190190540A1

    公开(公告)日：2019-06-20

    申请号：US16175567

    申请日：2018-10-30

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yukitoshi TSUBOI

    IPC: H03M13/29 ,  H03M13/00

    Abstract: The subject is to improve the detection performance in the error detection of data using an ECC. A data processing device 1 includes an encoder device 2 that includes an encoder unit to generate an ECC by performing operations according to a first ECC generation matrix and an encoder unit 5 to generate an ECC by performing operations according to a second ECC generation matrix obtained by permutating a column of the first ECC generation matrix. The encoder unit 4 generates the first ECC for the first data. The encoder unit 5 generates the second ECC for the second data obtained by permutating a bit of the first data.

    SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD 审中-公开

    公开(公告)号：US20170255509A1

    公开(公告)日：2017-09-07

    申请号：US15446501

    申请日：2017-03-01

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yukitoshi TSUBOI ,  Hiroyuki HAMASAKI

    IPC: G06F11/10

    CPC classification number: G06F11/1016 ,  G06F11/1044

    Abstract: The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

    MICROCOMPUTER
    6.
    发明申请
    MICROCOMPUTER 有权

    公开(公告)号：US20150019779A1

    公开(公告)日：2015-01-15

    申请号：US14328154

    申请日：2014-07-10

    Applicant: Renesas Electronics Corporation

    Inventor： Takuya HIRADE ,  Yukitoshi TSUBOI ,  Ryosuke OKUDA

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F11/2231 ,  G06F11/2273 ,  Y02D10/14

    Abstract: To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality.

    Abstract translation: 检测中断控制系统中的异常，而不用完全依赖于电路的二次化，而无需通过花费时间创建内置自检的测试模式，而不会大大增加功耗。 在从中断控制器到中央处理单元的中断信号系统中，使用定时器等周期性地生成测试中断请求，在中断处理程序中检查中断控制器内的中断请求标志的状态，在 检测到相同的中断请求标志被连续地保持在设定状态两次或更多的情况下，假设在中断信号系统中出现故障的可能性很高，并且认为存在 异常

    SEMICONDUCTOR DEVICE, DIAGNOSTIC TEST, AND DIAGNOSTIC TEST CIRCUIT
    8.
    发明申请
    SEMICONDUCTOR DEVICE, DIAGNOSTIC TEST, AND DIAGNOSTIC TEST CIRCUIT 审中-公开

    公开(公告)号：US20180080984A1

    公开(公告)日：2018-03-22

    申请号：US15800936

    申请日：2017-11-01

    Applicant: Renesas Electronics Corporation

    Inventor： Yukitoshi TSUBOI ,  Hideo NAGANO ,  Hiroshi NAGAOKA ,  Yusuke MATSUNAGA ,  Yutaka IGAKU ,  Naotaka KUBOTA

    IPC: G01R31/3177 ,  G06F11/08 ,  G01R31/3185

    Abstract: A semiconductor device includes a system bus, a plurality of Central Processing Unit (CPU) cores each connected to the system bus, including a scan chain, and being assigned one or more tasks and configured to perform one of the tasks in a normal operation state, and a diagnostic test circuit connected to the system bus and capable of communicating with the plurality of the CPU cores, and configured to perform a scan test for the plurality of the CPU cores by using the scan chain. The plurality of the CPU cores outputs a test start instruction signal to the diagnostic test circuit, when the test start instruction signal is output from one of the plurality of the CPU cores, the diagnostic test circuit performs a scan test for the one of the plurality of the CPU cores in accordance with the test start instruction signal.

    SEMICONDUCTOR DEVICE, DIAGNOSTIC TEST, AND DIAGNOSTIC TEST CIRCUIT
    9.
    发明申请
    SEMICONDUCTOR DEVICE, DIAGNOSTIC TEST, AND DIAGNOSTIC TEST CIRCUIT 有权
    半导体器件，诊断测试和诊断测试电路

    公开(公告)号：US20150293173A1

    公开(公告)日：2015-10-15

    申请号：US14676743

    申请日：2015-04-01

    Applicant: Renesas Electronics Corporation

    Inventor： Yukitoshi TSUBOI ,  Hideo NAGANO ,  Hiroshi NAGAOKA ,  Yusuke MATSUNAGA ,  Yutaka IGAKU ,  Naotaka KUBOTA

    IPC: G01R31/3177 ,  G06F11/08

    CPC classification number: G01R31/3177 ,  G01R31/318544 ,  G06F11/08

    Abstract: Deterioration in operation performance due to a fault diagnosis is prevented. A semiconductor device 90 according to the present invention includes a plurality of CPU cores 91 to 94 each including a scan chain, and a diagnostic test circuit 95 that performs a scan test for the plurality of CPU cores 91 to 94 by using the scan chain of the CPU core. The diagnostic test circuit 95 performs a scan test for each of the plurality of CPU cores 91 to 94 in a predetermined order on a periodic basis so that execution time periods of the scan tests do not overlap each other.

    Abstract translation: 防止由故障诊断引起的操作性能恶化。 根据本发明的半导体器件90包括多个包含扫描链的CPU核91至94，以及诊断测试电路95，其通过使用扫描链进行多个CPU核91至94的扫描测试 CPU内核。 诊断测试电路95以周期性的预定顺序对多个CPU核心91至94中的每一个执行扫描测试，使得扫描测试的执行时间周期彼此不重叠。

    SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND MEMORY ACCESS CONTROL METHOD 审中-公开

    公开(公告)号：US20190317854A1

    公开(公告)日：2019-10-17

    申请号：US16451915

    申请日：2019-06-25

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yukitoshi TSUBOI ,  Hiroyuki HAMASAKI

    IPC: G06F11/10

    Abstract: A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

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