公开(公告)号：US20140210002A1

公开(公告)日：2014-07-31

申请号：US14158707

申请日：2014-01-17

Applicant: ROHM CO., LTD.

Inventor： Kensuke SAWASE ,  Motohiro TOYONAGA

IPC: H01L29/78 ,  H01L27/06

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0922 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0865 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/665 ,  H01L29/7825 ,  H01L29/7833

Abstract: The n-channel double diffusion MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the p-type semiconductor substrate and the p-type epitaxial layer. In a p-type body layer provided in a surface portion of the p-type epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the p-type epitaxial layer in spaced relation from the p-type body layer. An n-type drain layer is provided in a surface portion of the p-type epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the p-type epitaxial layer between the n-type drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer.

Abstract translation: n沟道双扩散MOS晶体管包括p型半导体衬底，p型外延层和设置在p型半导体衬底和p型外延层之间的边界中的n型掩埋层。 在设置在p型外延层的表面部分的p型体层中，提供n型源极层以与p型体层一起限定双扩散结构。 在p型外延层的与p型体层隔开的表面部分设置有n型漂移层。 n型漏极层设置在与n型漂移层接触的p型外延层的表面部分中。 具有比n型掩埋层低的杂质浓度的p型掩埋层被埋在n型漂移层和n型掩埋层之间的p型外延层中，与n型掩埋层的上表面接触 型掩埋层。

公开(公告)号：US20160035885A1

公开(公告)日：2016-02-04

申请号：US14882411

申请日：2015-10-13

Applicant: ROHM CO., LTD.

Inventor： Kensuke SAWASE ,  Motohiro TOYONAGA

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0922 ,  H01L28/10 ,  H01L28/40 ,  H01L29/0865 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/665 ,  H01L29/7825 ,  H01L29/7833

Abstract: A MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the semiconductor substrate and the epitaxial layer. In a p-type body layer provided in a surface portion of the epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the epitaxial layer in spaced relation from the body layer. An n-type drain layer is provided in a surface portion of the epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the epitaxial layer between the drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer.

Abstract translation: MOS晶体管包括p型半导体衬底，p型外延层和设置在半导体衬底和外延层之间的边界中的n型掩埋层。 在设置在外延层的表面部分的p型体层中，设置n型源极层以与p型体层一起限定双扩散结构。 n型漂移层设置在与体层隔开的外延层的表面部分中。 n型漏极层设置在与n型漂移层接触的外延层的表面部分中。 与n型掩埋层的上表面接触的漂移层和n型掩埋层之间的外延层中埋设具有比n型埋层低的杂质浓度的p型掩埋层。

公开(公告)号：US20180020549A1

公开(公告)日：2018-01-18

申请号：US15646086

申请日：2017-07-10

Applicant: ROHM CO., LTD.

Inventor： Motohiro TOYONAGA ,  Yasuhiro FUWA ,  Mamoru YAMAGAMI ,  Isamu NISHIMURA

IPC: H05K1/18 ,  H01L23/13 ,  H01L23/31 ,  H05K1/11 ,  H05K3/00 ,  H01L23/00 ,  H05K1/02 ,  H05K3/28 ,  H01L21/48 ,  H01L23/498

CPC classification number: H05K1/186 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15156 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09018 ,  H05K2201/10636 ,  H05K2203/1316 ,  H01L2224/81 ,  H01L2924/014

Abstract: An electronic component includes a substrate including a first principal surface, a second principal surface positioned on a side opposite to the first principal surface, a first side surface that connects the first principal surface and the second principal surface and that extends along a first direction, a second side surface that connects the first principal surface and the second principal surface and that extends along a second direction intersecting the first direction, and a corner portion that connects the first side surface and the second side surface and that has a curved surface curved outwardly, and a chip arranged at the first principal surface of the substrate.