公开(公告)号：US20140315359A1

公开(公告)日：2014-10-23

申请号：US14323430

申请日：2014-07-03

Applicant: ROHM CO., LTD.

Inventor： Toshio NAKAJIMA

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7811 ,  H01L21/261 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/66712 ,  H01L29/7802

Abstract: A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.

Abstract translation: 半导体器件包括p型半导体层，由具有n型性质的柱状导热体形成的n型列区域，插入在n型列区域之间的p型列区域，n型列区域配置 与p型列区域形成超结结构，形成在半导体层中的沟道区域，形成在沟道区域中的源极区域，形成在半导体层上的栅极绝缘膜，以及形成的栅极电极 在栅极绝缘膜上并与栅极绝缘膜两端的沟道区相对。

公开(公告)号：US20130302957A1

公开(公告)日：2013-11-14

申请号：US13922441

申请日：2013-06-20

Applicant: Rohm Co., Ltd.

Inventor： Toshio NAKAJIMA

IPC: H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/263 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66712 ,  H01L29/7805

Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer o form a trap level locally.

Abstract translation: 一种半导体器件包括：第一基极层; 漏极层，设置在所述第一基底层的背面上; 形成在所述第一基底层的表面上的第二基底层; 源层，形成在第二基层的表面上; 设置在源极层和第二基极层的表面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 通过与漏极层相对，形成在第二基极层和源极层的下部的第一基底层中的列层; 设置在所述漏极层中的漏电极; 以及设置在所述源极层和所述第二基底层两者上的源电极，其中对所述列层O进行重粒子照射，形成局部的阱层级。

公开(公告)号：US20210098570A1

公开(公告)日：2021-04-01

申请号：US17032224

申请日：2020-09-25

Applicant: ROHM Co., LTD.

Inventor： Yuto OSAWA ,  Toshio NAKAJIMA ,  Shuta KOJIMA

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

Abstract: Disclosed is a semiconductor device including a semiconductor layer having a main surface, a first conductivity type drift region formed at a surface layer part of the main surface, a super junction region having a first conductivity type first column region and a second conductivity type second column region, a second conductivity type low resistance region formed at the surface layer part of the drift region and having an impurity concentration in excess of that of the second column region, a region insulating layer formed on the main surface and covering the low resistance region such as to cause part of the low resistance region to be exposed, a first pad electrode formed on the region insulating layer such as to overlap with the low resistance region, and a second pad electrode formed on the main surface and electrically connected to the second column region and the low resistance region.

公开(公告)号：US20190148536A1

公开(公告)日：2019-05-16

申请号：US16245681

申请日：2019-01-11

Applicant: ROHM CO., LTD.

Inventor： Toshio NAKAJIMA

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/32 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

公开(公告)号：US20160035824A1

公开(公告)日：2016-02-04

申请号：US14876795

申请日：2015-10-06

Applicant: ROHM CO., LTD.

Inventor： Toshio NAKAJIMA

IPC: H01L29/06 ,  H01L21/265 ,  H02P27/06 ,  H01L27/088 ,  H02M7/5387 ,  H02P6/14 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L29/7802 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/32 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827 ,  H02M7/5387 ,  H02P6/14 ,  H02P27/06

Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.

公开(公告)号：US20150279932A1

公开(公告)日：2015-10-01

申请号：US14739061

申请日：2015-06-15

Applicant: ROHM CO., LTD.

Inventor： Toshio NAKAJIMA

IPC: H01L29/06 ,  H02M7/5387 ,  H02P6/14 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/32 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827 ,  H02M7/5387 ,  H02P6/14 ,  H02P27/06

Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.

公开(公告)号：US20160284835A1

公开(公告)日：2016-09-29

申请号：US15173652

申请日：2016-06-04

Applicant: ROHM CO., LTD.

Inventor： Toshio NAKAJIMA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L21/263 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/66712 ,  H01L29/7805

Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

Abstract translation: 一种半导体器件包括：第一基极层; 漏极层，设置在所述第一基底层的背面上; 形成在所述第一基底层的表面上的第二基底层; 源层，形成在第二基层的表面上; 设置在源极层和第二基极层的表面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 通过与漏极层相对，形成在第二基极层和源极层的下部的第一基底层中的列层; 设置在所述漏极层中的漏电极; 以及设置在所述源极层和所述第二基极层两者上的源电极，其中对所述列层进行重粒子照射以局部形成陷阱电平。

公开(公告)号：US20150221763A1

公开(公告)日：2015-08-06

申请号：US14683203

申请日：2015-04-10

Applicant: ROHM CO., LTD.

Inventor： Toshio NAKAJIMA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/167 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L21/261 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/66712 ,  H01L29/7802

Abstract: A semiconductor device includes a p-type semiconductor layer, n-type column regions formed of columnar thermal donors exhibiting an n-type property, a p-type column region interposed between the n-type column regions, the n-type column regions configured to form a super-junction structure in cooperation with the p-type column region, a channel region formed in the semiconductor layer, a source region formed in the channel region, a gate insulator film formed on the semiconductor layer, and a gate electrode formed on the gate insulator film and opposite to the channel region across the gate insulator film.

Abstract translation: 半导体器件包括p型半导体层，由具有n型性质的柱状导热体形成的n型列区域，插入在n型列区域之间的p型列区域，n型列区域配置 与p型列区域形成超结结构，形成在半导体层中的沟道区域，形成在沟道区域中的源极区域，形成在半导体层上的栅极绝缘膜，以及形成的栅极电极 在栅极绝缘膜上并与栅极绝缘膜两端的沟道区相对。

公开(公告)号：US20150140754A1

公开(公告)日：2015-05-21

申请号：US14569821

申请日：2014-12-15

Applicant: ROHM CO., LTD.

Inventor： Toshio NAKAJIMA

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7802 ,  H01L21/263 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/32 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827 ,  H02M7/5387 ,  H02P6/14 ,  H02P27/06

Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.

Abstract translation: 半导体器件包括n型漏极层，设置在n型漏极层上的n型基极层，部分地形成在n型漏极层的表面层部分中的p型基极层和n型源极层 基极层和p型基极层，形成在n型源极层和n型基极层之间的p型基极层的表面上的栅极绝缘膜，形成在栅极绝缘体上的栅电极 覆盖栅极绝缘膜的p型基底层的膜，从n型基极层形成的p型列层，从p型基极层朝向n型漏极层延伸，耗尽层缓和区域 布置在p型列层和n型漏极层之间，并且包括转换为馈电体的第一重子，连接到n型源极层的源电极和连接到n型漏极层的漏电极。

公开(公告)号：US20200251410A1

公开(公告)日：2020-08-06

申请号：US16853302

申请日：2020-04-20

Applicant: ROHM CO., LTD.

Inventor： Yasumasa KASUYA ,  Hiroaki MATSUBARA ,  Hiroshi KUMANO ,  Toshio NAKAJIMA ,  Shigeru HIRATA ,  Yuji ISHIMATSU

IPC: H01L23/495 ,  H01L29/78 ,  H01L29/08 ,  H01L23/00 ,  H02P6/12 ,  H02P6/14

Abstract: A power module includes a first die pad, a first switching element, a second die pad, a second switching element, an integrated circuit element, an encapsulation resin, and a lead frame assembly. The encapsulation resin encapsulates the first switching element, the second switching element, and the integrated circuit element. The lead frame assembly includes an outer lead and an inner lead. The lead frame assembly includes a first lead frame and a second lead frame. The first lead frame includes a first inner lead connected to the first die pad and a first outer lead connected to the first inner lead. The second lead frame includes a second inner lead connected to the second die pad and a second outer lead connected to the second inner lead.