公开(公告)号：US5955751A

公开(公告)日：1999-09-21

申请号：US133999

申请日：1998-08-13

申请人： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

发明人： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

IPC分类号： H01L23/525 ,  H01L23/52 ,  H01L23/528

CPC分类号： H01L23/5252 ,  H01L23/525 ,  H01L2924/0002

摘要： A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. In some embodiments, less than seventy-five percent of all antifuses of the field programmable gate array have an edge of the region of programmable material disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. Other antifuse structures and methods are also disclosed for preventing programmable material corners and/or edges from compromising yield and/or reliability of programmable devices.

公开(公告)号：US06627969B1

公开(公告)日：2003-09-30

申请号：US09563091

申请日：2000-05-01

申请人： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

发明人： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

IPC分类号： H01L2900

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal-to-metal conductive plug-type antifuse has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor. The airbreak may stuff grain boundaries in the upper surface of the first barrier metal and/or may cause the first barrier metal layer to have different grains and/or a different grain orientation than the overlaying second barrier metal layer. In some embodiments, a capping layer over the top surface of the programmable material protects the underlying programmable material during an ashing step when a mask used to etch the programmable material is removed. The capping layer and the programmable material form a capping layer/programmable material layer stack within the antifuse underneath the two barrier metal layers. The capping layer may also be made of a barrier metal and constitute an additional barrier.

摘要翻译： 金属对金属导电塞型反熔丝具有设置在绝缘层的开口中的导电插塞。 可编程材料特征（例如，非晶硅）覆盖在导电插塞上。 涉及在可编程材料中迁移的金属（例如铝或铜）的导体覆盖在可编程材料上。 为了防止当反熔丝未编程时金属从导体迁移到可编程材料中，导体在迁移的金属和可编程材料之间具有一层阻挡金属。 在一些实施例中，存在两层屏障金属。 在形成第一阻挡金属层之后的空气破裂提高了阻挡金属防止可编程材料与上覆导体之间的扩散的能力。 所述防风剂可以在第一阻挡金属的上表面填充晶界，和/或可使第一阻挡金属层与覆盖的第二阻挡金属层具有不同的晶粒和/或不同的晶粒取向。 在一些实施例中，当可去除用于蚀刻可编程材料的掩模时，可编程材料顶表面上的覆盖层在灰化步骤期间保护底层可编程材料。 封盖层和可编程材料在两个阻挡金属层下面的反熔丝内形成覆盖层/可编程材料层堆叠。 封盖层也可以由阻挡金属制成并构成另外的屏障。

公开(公告)号：US06107165A

公开(公告)日：2000-08-22

申请号：US133998

申请日：1998-08-13

申请人： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

发明人： Rajiv Jain ,  Andre Stolmeijer ,  Mehul D. Shroff

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002

摘要： A metal-to-metal conductive plug-type antifuise has a conductive plug disposed in an opening in an insulating layer. A programmable material feature (for example, amorphous silicon) overlies the conductive plug. A conductor involving a metal (for example, aluminum or copper) that migrates in the programmable material overlies the programmable material. To prevent migration of metal from the conductor into the programmable material when the antifuse is not programmed, the conductor has a layer of barrier metal between the metal that migrates and the programmable material. In some embodiments, there are two layers of barrier metal. An airbreak after formation of the first barrier metal layer improves the ability of the barrier metal to prevent diffusion between the programmable material and the overlying conductor. The airbreak may stuff grain boundaries in the upper surface of the first barrier metal and/or may cause the first barrier metal layer to have different grains and/or a different grain orientation than the overlaying second barrier metal layer. In some embodiments, a capping layer over the top surface of the programmable material protects the underlying programmable material during an ashing step when a mask used to etch the programmable material is removed. The capping layer and the programmable material form a capping layer/programmable material layer stack within the antifuse underneath the two barrier metal layers. The capping layer may also be made of a barrier metal and constitute an additional barrier.

摘要翻译： 金属对金属导电插塞型防腐剂具有设置在绝缘层的开口中的导电插塞。 可编程材料特征（例如，非晶硅）覆盖在导电插塞上。 涉及在可编程材料中迁移的金属（例如铝或铜）的导体覆盖在可编程材料上。 为了防止当反熔丝未编程时金属从导体迁移到可编程材料中，导体在迁移的金属和可编程材料之间具有一层阻挡金属。 在一些实施例中，存在两层屏障金属。 在形成第一阻挡金属层之后的空气破裂提高了阻挡金属防止可编程材料与上覆导体之间的扩散的能力。 所述防风剂可以在第一阻挡金属的上表面填充晶界，和/或可使第一阻挡金属层与覆盖的第二阻挡金属层具有不同的晶粒和/或不同的晶粒取向。 在一些实施例中，当可去除用于蚀刻可编程材料的掩模时，可编程材料顶表面上的覆盖层在灰化步骤期间保护底层可编程材料。 封盖层和可编程材料在两个阻挡金属层下面的反熔丝内形成覆盖层/可编程材料层堆叠。 封盖层也可以由阻挡金属制成并构成另外的屏障。

公开(公告)号：US6154054A

公开(公告)日：2000-11-28

申请号：US309165

申请日：1999-05-10

申请人： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

发明人： Mehul D. Shroff ,  Rajiv Jain ,  Andre Stolmeijer ,  Kathryn E. Gordon

IPC分类号： H01L23/525 ,  H03K19/177

CPC分类号： H01L23/5252 ,  H01L23/525 ,  H01L2924/0002

摘要： A field programmable gate array has antifuses disposed over logic modules. Each of these antifuses includes a conductive plug and an overlaying region of programmable material (for example, amorphous silicon). To program one of these antifuses, an electric connection is formed through the programmable material to couple the conductive plug to a metal conductor that overlays the region of programmable material. The metal conductor includes a layer of a barrier metal to separate another metal of the conductor (for example, aluminum from an aluminum layer) from migrating into the programmable material when the antifuse is unprogrammed. In some embodiments, less than three percent of all antifuses of the field programmable gate array has a corner (from the top-down perspective) of the region of programmable material that is disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. In some embodiments, less than seventy-five percent of all antifuses of the field programmable gate array have an edge of the region of programmable material disposed (within lateral distance DIS of the conductive plug) underneath the metal conductor of that antifuse. Other antifuse structures and methods are also disclosed for preventing programmable material corners and/or edges from compromising yield and/or reliability of programmable devices.

摘要翻译： 现场可编程门阵列具有置于逻辑模块上的反熔丝。 这些反熔丝中的每一个包括导电插塞和可编程材料（例如，非晶硅）的覆盖区域。 为了编程这些反熔丝之一，通过可编程材料形成电连接，以将导电插塞耦合到覆盖可编程材料区域的金属导体。 当反熔丝未编程时，金属导体包括隔离金属层，以将导体的另一金属（例如铝从铝层分离）迁移到可编程材料中。 在一些实施例中，现场可编程门阵列的所有反熔丝的小于3％具有可编程材料区域（在导电插塞的横向距离DIS内）（在金属的下侧视角内）的拐角（在导电插塞的横向距离DIS内） 该反熔丝的导体。 在一些实施例中，现场可编程门阵列的所有反熔丝的小于百分之七十五的边缘都是在该反熔丝的金属导体之下设置（在导电插塞的横向距离DIS内）的可编程材料区域的边缘。 还公开了其他反熔丝结构和方法，用于防止可编程材料拐角和/或边缘损害可编程器件的产量和/或可靠性。

公开(公告)号：US06509209B1

公开(公告)日：2003-01-21

申请号：US09697706

申请日：2000-10-25

申请人： Mehul D. Shroff ,  Rajiv Jain

发明人： Mehul D. Shroff ,  Rajiv Jain

IPC分类号： H01L2182

CPC分类号： H01L23/564 ,  H01L21/7681 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.

摘要翻译： 反熔丝设置在第一和第二导体之间。 绝缘扩散阻挡层（例如，氮化硅）覆盖反熔丝的侧壁以阻止污染物（例如铜，氯，氟，钠，钾和水分）从层间电介质横向扩散到反熔丝中，其中 镶嵌铜导体和/或低k电介质。 在镶嵌反熔丝结构中，绝缘扩散阻挡层覆盖未被反熔丝覆盖的镶嵌导体的上表面。 该绝缘扩散阻挡层抑制铜扩散到层间电介质中，然后横向扩散到反熔丝中。

公开(公告)号：US06515343B1

公开(公告)日：2003-02-04

申请号：US09196946

申请日：1998-11-19

申请人： Mehul D. Shroff ,  Rajiv Jain

发明人： Mehul D. Shroff ,  Rajiv Jain

IPC分类号： H01L2900

CPC分类号： H01L23/564 ,  H01L21/7681 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse is disposed between a first and second conductor. An insulating diffusion barrier (for example, silicon nitride) covers the sidewalls of the antifuse to inhibit contaminants (for example, copper, chlorine, fluorine, sodium, potassium, and moisture) from diffusing laterally into the antifuse from the interlayer dielectric, where a damascene copper conductor and/or a low-k dielectric is used. In a damascene antifuse structure, the insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then diffusing laterally into the antifuse.

摘要翻译： 反熔丝设置在第一和第二导体之间。 绝缘扩散阻挡层（例如，氮化硅）覆盖反熔丝的侧壁以阻止污染物（例如铜，氯，氟，钠，钾和水分）从层间电介质横向扩散到反熔丝中，其中 镶嵌铜导体和/或低k电介质。 在镶嵌反熔丝结构中，绝缘扩散阻挡层覆盖未被反熔丝覆盖的镶嵌导体的上表面。 该绝缘扩散阻挡层抑制铜扩散到层间电介质中，然后横向扩散到反熔丝中。

公开(公告)号：US09685405B2

公开(公告)日：2017-06-20

申请号：US13907497

申请日：2013-05-31

申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

IPC分类号： H01L23/525 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L23/5256 ,  H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

公开(公告)号：US20150348898A1

公开(公告)日：2015-12-03

申请号：US14292886

申请日：2014-05-31

申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  G06F17/50

CPC分类号： H01L23/5283 ,  G06F17/5077 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

摘要翻译： 用于选择集成电路装置中用于放置应力源以管理电迁移故障的位置的方法包括计算集成电路装置内的互连的电流，并基于电流确定互连的电迁移应力分布。 该方法还包括确定互连上的区域以放置应力源以改变互连的电迁移应力分布。

公开(公告)号：US20150279854A1

公开(公告)日：2015-10-01

申请号：US14228678

申请日：2014-03-28

申请人： MARK D. HALL ,  Mehul D. Shroff

发明人： MARK D. HALL ,  Mehul D. Shroff

IPC分类号： H01L27/115 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3105 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L27/11568 ,  H01L21/31051 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

摘要翻译： 在NVM区域和使用半导体衬底的逻辑区域中形成半导体器件包括形成电介质层并在电介质层上形成第一栅极材料层。 在逻辑区域中，形成高k电介质和阻挡层。 在阻挡层和第一材料层之上形成第二栅极材料层。 图案化导致NVM区域上的栅极区域填充材料和包括第二栅极材料层的一部分和逻辑区域中的势垒层的一部分的逻辑堆叠。 栅极填充材料中的开口离开由与开口相邻的栅极 - 区域填充材料的一部分形成的选择栅极。 在电荷存储层上的开口中形成控制栅极。 第二栅极材料层的部分被金属逻辑门替代。

公开(公告)号：US20150234961A1

公开(公告)日：2015-08-20

申请号：US14558694

申请日：2014-12-02

申请人： Zhichen Zhang ,  Xavier Hours ,  Mehul D. Shroff ,  Chuanzheng Wang ,  Qilin Zhang

发明人： Zhichen Zhang ,  Xavier Hours ,  Mehul D. Shroff ,  Chuanzheng Wang ,  Qilin Zhang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/76

摘要： A method for integrated circuit reliability aging simulation includes dividing a target time period into N stages including a first stage and a second stage; obtaining first parameter values of a reliability model for the first stage; performing a first simulation on the circuit based on the reliability model and the first parameter values to obtain first aging results; obtaining second parameter values of the reliability model for the second stage; and performing a second simulation on the circuit based on the reliability model and the second parameter values to obtain second aging results.

摘要翻译： 一种用于集成电路可靠性老化模拟的方法，包括将目标时间段划分为包括第一阶段和第二阶段的N个阶段; 获得第一阶段的可靠性模型的第一参数值; 基于可靠性模型和第一参数值在电路上执行第一模拟以获得第一老化结果; 获得第二阶段的可靠性模型的第二参数值; 以及基于所述可靠性模型和所述第二参数值在所述电路上执行第二仿真以获得第二老化结果。