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公开(公告)号：US09087603B2
公开(公告)日：2015-07-21
申请号：US12369105
申请日：2009-02-11
申请人： Randy B. Osborne
发明人： Randy B. Osborne
IPC分类号： G11C8/00 , G11C11/4094 , G11C7/10 , G11C8/18
CPC分类号： G11C11/4094 , G11C7/1012 , G11C8/18
摘要： Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.
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公开(公告)号：US07673111B2
公开(公告)日：2010-03-02
申请号：US11318028
申请日：2005-12-23
申请人： Shelley Chen , Randy B. Osborne
发明人： Shelley Chen , Randy B. Osborne
CPC分类号： G06F13/1642 , Y02D10/14
摘要： In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.
摘要翻译： 在一些实施例中，芯片包括包括写入请求的请求队列，以及调度电路来调度包括响应于写入请求的命令的命令。 芯片还包括模式选择电路，用于监视请求队列并响应于此选择用于调度电路的第一或第二模式，其中在第一模式中，调度电路将某些命令调度为单独的单个命令，并且在第二模式中 调度电路安排统一的命令来表示多个独立的单个命令。 描述其他实施例。
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公开(公告)号：US07167946B2
公开(公告)日：2007-01-23
申请号：US10676882
申请日：2003-09-30
申请人： Randy B. Osborne
发明人： Randy B. Osborne
IPC分类号： G06F12/00
CPC分类号： G11C11/4094 , G11C11/4076
摘要： Apparatus and method to implicitly transmit a command to close a row of memory cells within a memory device as part of the transmission of an activate command to open another row of memory cells within the memory device.
摘要翻译： 用于隐藏地发送命令以关闭存储器设备内的一行存储器单元的装置和方法，作为激活命令的传输的一部分，以打开存储器设备内的另一行存储器单元。
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公开(公告)号：US06983356B2
公开(公告)日：2006-01-03
申请号：US10325795
申请日：2002-12-19
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F2212/502 , G06F2212/6022
摘要： A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.
摘要翻译： 从存储器件预取的方法包括确定预取缓冲器命中率（PBHR）和存储器带宽利用率（MBU）速率。 如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）高于PBHR阈值级别，则会大大插入预取。 如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）低于PBHR阈值级别，则保留预存取值。
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5.发明授权公开(公告)号：US06941425B2
公开(公告)日：2005-09-06
申请号：US10010994
申请日：2001-11-12
申请人： Randy B. Osborne
发明人： Randy B. Osborne
CPC分类号： G06F13/1626 , G06F13/161
摘要： A method and apparatus for the optimization of memory read operations via read launch optimizations in memory interconnect are disclosed. In one embodiment, a write request may be preempted by a read request.
摘要翻译： 公开了一种通过存储器互连中的读取启动优化优化存储器读取操作的方法和装置。 在一个实施例中，写请求可以被读请求抢占。
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公开(公告)号：US6008813A
公开(公告)日：1999-12-28
申请号：US905238
申请日：1997-08-01
CPC分类号： G06T15/08 , G06T1/60 , G06T15/005 , G06T15/40
摘要： Apparatus is provided to enable real-time volume rendering on a personal computer or a desktop computer in which a technique involving blocking of voxel data organizes the data so that all voxels within a block are stored at consecutive memory addresses within a single memory model, making possible fetching an entire block of data in a burst rather than one voxel at a time. This permits utilization of DRAM memory modules which provide high capacity and low cost with substantial space savings. Additional techniques including sectioning reduces the amount of intermediate storage in a processing pipeline to an acceptable level for semiconductor implementation. A multiplexing technique takes advantage of blocking to reduce the amount of data needed to be transmitted per block, thus reducing the number of pins and the rates at which data must be transmitted across the pins connecting adjacent processing modules with each other. A mini-blocking technique saves the time needed to process sections by avoiding reading entire blocks for voxels near the boundary between a section and previously processed sections.
摘要翻译： 提供了一种用于在个人计算机或台式计算机上实时体积渲染的装置，其中涉及阻塞体素数据的技术组织数据，使得块内的所有体素被存储在单个存储器模型内的连续存储器地址处，使得 一次可能在突发而不是一个体素中获取整个数据块。 这允许利用提供高容量和低成本的DRAM存储器模块，同时节省了大量空间。 包括切片的其他技术将处理管线中的中间存储量减少到半导体实现的可接受水平。 复用技术利用阻塞来减少每个块需要传输的数据量，从而减少引脚数量和数据必须在连接相邻处理模块的引脚之间传输的速率。 微型阻塞技术通过避免读取部分和先前处理的部分之间边界附近的体素的整个块来节省处理部分所需的时间。
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7.发明授权Computer network interface and network protocol with direct deposit messaging 失效计算机网络接口和网络协议，具有直接存取信息
公开(公告)号：US5790804A
公开(公告)日：1998-08-04
申请号：US596708
申请日：1996-02-05
申请人： Randy B. Osborne
发明人： Randy B. Osborne
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5652
摘要： A network protocol and interface using direct deposit messaging provides low overhead communication in a network of multi-user computers. This system uses both sender-provided and receiver-provided information to process received messages and to deposit data directly in memory and to conditionally interrupt a host processor based on control information. Message processing is separated into data delivery, which bypasses the host processor and operating system, and message actions which may or may not require host processor interaction. In this protocol, a message includes an indication of the operation desired by the sender, an operand specified by the sender and an operand which refers to some information stored at the receiver. The receiver ensures that the desired action is permitted and then, if the action is permitted, performs the action according to both the operand specified by the sender and the state of the receiver. The action may be message delivery, wherein the operands in the message specify values for use in various addressing modes including direct, indirect, post-increment and index modes. The action may also be conditionally generating an interrupt, wherein the operands are used, in combination with the receiver state, to determine whether a message requires immediate or delayed action. The action may also be an operation on a register in the network interface or on other information stored at the receiver.
摘要翻译： 使用直接存取消息的网络协议和接口在多用户计算机的网络中提供低开销通信。 该系统使用发送者提供的和接收者提供的信息来处理接收到的消息并且将数据直接存储在存储器中并且基于控制信息有条件地中断主机处理器。 消息处理分为数据传送，绕过主机处理器和操作系统，以及可能需要或可能不需要主机处理器交互的消息动作。 在该协议中，消息包括发送者期望的操作的指示，由发送者指定的操作数和引用存储在接收者处的一些信息的操作数。 接收器确保允许所需的动作，然后如果允许动作，则根据发送方指定的操作数和接收方的状态执行动作。 该动作可以是消息传递，其中消息中的操作数指定用于各种寻址模式的值，包括直接，间接，后递增和索引模式。 该动作还可以有条件地产生中断，其中与接收器状态结合使用操作数来确定消息是否需要立即或延迟动作。 该动作也可以是网络接口中的寄存器或存储在接收器处的其他信息上的操作。
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8.发明授权On-package input/output clustered interface having full and half-duplex modes 有权集成式输入/输出集群接口，具有全双工和半双工模式公开(公告)号：US08902956B2
公开(公告)日：2014-12-02
申请号：US13995015
申请日：2011-12-22
IPC分类号： H04B1/38 , H04B3/02 , G06F15/78 , G06F13/40 , H03K19/0175
CPC分类号： G06F13/4068 , G06F13/4086 , G06F15/7825 , H03K19/017545 , H04B3/02 , H04B14/023
摘要： An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.
摘要翻译： 一种用于控制片上网络流量的装置和系统。 该装置的实施例包括在第一芯片上用于与第二芯片耦合的单端传输电路和单端接收电路，所述传输电路具有阻抗匹配和缺少均衡，接收电路缺少均衡，传输电路和接收电路 具有静态可配置的特征并且被组织成簇，其中所述簇具有用于不同配置的可配置特征的相同的物理层电路设计，所述可配置特征包括半双工模式和全双工模式，其中第一芯片和第二芯片是 在相同的封装上，并且其中用于将第一芯片与第二芯片耦合的多条导线匹配。
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公开(公告)号：US20100122046A1
公开(公告)日：2010-05-13
申请号：US12690551
申请日：2010-01-20
IPC分类号： G06F12/02
CPC分类号： G06F13/1684 , G09G5/393 , G09G2360/122 , G09G2360/125
摘要： According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel. The transaction assembler combines the request into one or more additional requests to access two or more independently addressable subchannels within the channel.
摘要翻译： 根据一个实施例，公开了一种存储器控制器。 存储器控制器包括分配逻辑和事务汇编器。 分配逻辑接收访问存储器通道的请求。 交易汇编器将该请求组合成一个或多个附加请求以访问频道内的两个或更多个可独立寻址的子信道。
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公开(公告)号：US07127574B2
公开(公告)日：2006-10-24
申请号：US10692245
申请日：2003-10-22
IPC分类号： G06F12/02
CPC分类号： G06F13/1631
摘要： Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.
摘要翻译： 本发明的实施例提供了一种用于将读取和写入事务调度到存储器的算法，以改进命令和数据总线利用率并在一系列工作负载上获得性能的算法。 特别地，存储器事务被排序成队列，使得它们不具有彼此的页冲突，并且根据读和写调度算法从这些队列排序排序以优化等待时间。
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