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    On-package input/output clustered interface having full and half-duplex modes
    1.
    发明授权
    On-package input/output clustered interface having full and half-duplex modes 有权
    集成式输入/输出集群接口，具有全双工和半双工模式

    公开(公告)号：US08902956B2

    公开(公告)日：2014-12-02

    申请号：US13995015

    申请日：2011-12-22

    申请人： Thomas P. Thomas ,  Stanley S. Kulick ,  Randy B. Osborne

    发明人： Thomas P. Thomas ,  Stanley S. Kulick ,  Randy B. Osborne

    IPC分类号： H04B1/38 ,  H04B3/02 ,  G06F15/78 ,  G06F13/40 ,  H03K19/0175

    CPC分类号： G06F13/4068 ,  G06F13/4086 ,  G06F15/7825 ,  H03K19/017545 ,  H04B3/02 ,  H04B14/023

    摘要： An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.

    摘要翻译： 一种用于控制片上网络流量的装置和系统。 该装置的实施例包括在第一芯片上用于与第二芯片耦合的单端传输电路和单端接收电路，所述传输电路具有阻抗匹配和缺少均衡，接收电路缺少均衡，传输电路和接收电路 具有静态可配置的特征并且被组织成簇，其中所述簇具有用于不同配置的可配置特征的相同的物理层电路设计，所述可配置特征包括半双工模式和全双工模式，其中第一芯片和第二芯片是 在相同的封装上，并且其中用于将第一芯片与第二芯片耦合的多条导线匹配。

    MECHANISMS FOR CLOCK GATING
    3.
    发明申请
    MECHANISMS FOR CLOCK GATING 有权
    时钟效应机制

    公开(公告)号：US20140009195A1

    公开(公告)日：2014-01-09

    申请号：US13997840

    申请日：2011-12-22

    申请人： Randy B. Osborne ,  Stanley S. Kulick ,  Erin Francom ,  Thomas P. Thomas

    发明人： Randy B. Osborne ,  Stanley S. Kulick ,  Erin Francom ,  Thomas P. Thomas

    IPC分类号： H03K5/15

    CPC分类号： H03K5/15 ,  G06F1/06 ,  G06F1/10 ,  G06F1/32

    摘要： Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package. Gating elements within the clock signal distribution network disable the clock signal to one or more portions of the clock signal distribution network. A digital locked loop (DLL) maintains settings without tracking when the clock signal is disabled.

    摘要翻译： 时钟门控机制 时钟发生电路通过集成电路封装内的时钟信号分配网络提供时钟信号。 时钟信号分配网络内的选通元件将时钟信号禁止到时钟信号分配网络的一个或多个部分。 数字锁定环（DLL）在禁止时钟信号时保持设置而不进行跟踪。

    ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DUPLEX MODES
    4.
    发明申请
    ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DUPLEX MODES 有权
    具有全双工模式的封装输入/输出集群接口

    公开(公告)号：US20130322556A1

    公开(公告)日：2013-12-05

    申请号：US13995015

    申请日：2011-12-22

    申请人： Thomas P. Thomas ,  Stanley S. Kulick ,  Randy B. Osborne

    发明人： Thomas P. Thomas ,  Stanley S. Kulick ,  Randy B. Osborne

    IPC分类号： G06F13/40 ,  H04B3/02

    CPC分类号： G06F13/4068 ,  G06F13/4086 ,  G06F15/7825 ,  H03K19/017545 ,  H04B3/02 ,  H04B14/023

    摘要： An apparatus and system for controlling traffic on an on-chip network. Embodiments of the apparatus comprise single-ended transmission circuitry and single-ended receiving circuitry on a first chip for coupling with a second chip, the transmission circuitry having impedance matching and lacking equalization, the receiving circuitry lacking equalization, the transmission circuitry and the receiving circuitry having statically configurable features and organized in clusters, wherein the clusters have the same physical layer circuitry design for different configurations of the configurable features, the configurable features including half-duplex mode and full-duplex mode, wherein the first chip and the second chip are on the same package, and wherein a plurality of conductive lines for coupling the first chip with the second chip are matched.

    摘要翻译： 一种用于控制片上网络流量的装置和系统。 该装置的实施例包括在第一芯片上用于与第二芯片耦合的单端传输电路和单端接收电路，所述传输电路具有阻抗匹配和缺少均衡，接收电路缺少均衡，传输电路和接收电路 具有静态可配置特征并且被组织成群集，其中所述簇具有用于不同配置的可配置特征的相同物理层电路设计，所述可配置特征包括半双工模式和全双工模式，其中所述第一芯片和所述第二芯片是 在相同的封装上，并且其中用于将第一芯片与第二芯片耦合的多条导线匹配。

    Phase frequency detector
    10.
    发明授权
    Phase frequency detector 失效
    相频检测器

    公开(公告)号：US06741102B1

    公开(公告)日：2004-05-25

    申请号：US09300757

    申请日：1999-04-26

    申请人： Thomas P. Thomas

    发明人： Thomas P. Thomas

    IPC分类号： H03L7089

    CPC分类号： H03L7/089 ,  H03D13/004 ,  H03L7/183

    摘要： Briefly, in accordance with one embodiment, an integrated circuit includes a phase-frequency detector (PFD) including two clock input ports, an up signal port and a down signal port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up output signal pulse and a down output signal pulse based, at least in part, upon the magnitude of an amount of phase delay between two respective clock signal pulses applied to the two input ports. Of course, additional embodiments are also disclosed.

    摘要翻译： 简而言之，根据一个实施例，集成电路包括包括两个时钟输入端口，上行信号端口和下行信号端口的相位频率检测器（PFD）。 PFD包括数字电路，其包括以配置来耦合的晶体管，以至少部分地基于两个相应时钟信号之间的相位延迟量的大小来调整上输出信号脉冲和下输出信号脉冲的重叠量 施加到两个输入端口的脉冲。 当然，还公开了另外的实施例。