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    High performance memory device-state aware chipset prefetcher
    1.
    发明授权
    High performance memory device-state aware chipset prefetcher 失效
    高性能存储器件状态感知芯片组预取器

    公开(公告)号：US06983356B2

    公开(公告)日：2006-01-03

    申请号：US10325795

    申请日：2002-12-19

    申请人： Hemant G. Rotithor ,  Randy B. Osborne ,  Donald W. McCauley

    发明人： Hemant G. Rotithor ,  Randy B. Osborne ,  Donald W. McCauley

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F12/0215 ,  G06F2212/502 ,  G06F2212/6022

    摘要： A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.

    摘要翻译： 从存储器件预取的方法包括确定预取缓冲器命中率（PBHR）和存储器带宽利用率（MBU）速率。 如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）高于PBHR阈值级别，则会大大插入预取。 如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）低于PBHR阈值级别，则保留预存取值。

    DATA CACHE PREFETCH HINTS
    2.
    发明申请
    DATA CACHE PREFETCH HINTS 有权

    公开(公告)号：US20140052927A1

    公开(公告)日：2014-02-20

    申请号：US13588622

    申请日：2012-08-17

    申请人： Donald W. McCauley ,  Stephen P. Thompson

    发明人： Donald W. McCauley ,  Stephen P. Thompson

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/6028

    摘要： The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.

    摘要翻译： 本发明提供一种使用预取提示的方法和装置。 该方法的一个实施例包括在与第一高速缓存相关联的第一预取器处旁路发出从由第一预取器确定的存储器地址序列中的多个存储器地址中预取数据的请求。 在从与第二高速缓存相关联的第二预取器接收的请求中指示该号码。 该方法的该实施例还包括从第一预取器发出在旁路存储器地址之后从存储器地址预取数据的请求。

    Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens
    3.
    发明授权
    Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens 失效
    由PT处理器执行页面数据传输，并由排队令牌协调的CPU发出拆分启动和测试指令

    公开(公告)号：US5386560A

    公开(公告)日：1995-01-31

    申请号：US704559

    申请日：1991-05-23

    申请人： Donald W. McCauley ,  Richard J. Schmalz ,  Ronald M. Smith, Sr. ,  Susan B. Stillman

    发明人： Donald W. McCauley ,  Richard J. Schmalz ,  Ronald M. Smith, Sr. ,  Susan B. Stillman

    IPC分类号： G06F13/42 ,  G06F12/02 ,  G06F13/16 ,  G06F15/17 ,  G06F13/14

    CPC分类号： G06F15/17 ,  G06F13/1642

    摘要： Asynchronously transfers blocks of data (called pages) between two different electronic media of a data processing system. The different media may be a system main storage and a system expanded storage or a non-volatile external type of storage, either of which use different addressing than the main storage. All of these storages may be made of DRAM or SRAM technology with battery backup when necessary. The invention splits the involvement of a program requesting a page transfer into a pair of instructions per page transfer executing on one or more central processors. The first instruction of a pair starts another processor that controls the asynchronous page transfer, and the second instruction of the pair enables the communication of the end of the page transfer to the program. Neither instruction in the pair interrupts the program for the page transfer. A processor executing the starting instruction is immediately free to execute any other available instructions. Although both instructions in a pair may be executed by one processor, the pair may be executed by separate processors. And the execution of other instructions may overlap the page transfer between the execution of the pair.

    摘要翻译： 在数据处理系统的两个不同电子介质之间异步传输数据块（称为页）。 不同的媒体可以是系统主存储和系统扩展存储或非易失性外部类型的存储，其中任何一种使用与主存储不同的寻址。 所有这些存储器可以由DRAM或SRAM技术制成，并在需要时进行电池备份。 本发明将请求页面传送的程序的参与划分为在一个或多个中央处理器上执行的每页传送的一对指令。 一对的第一条指令启动另一个控制异步页面传输的处理器，该对的第二条指令使页面传送结束的通信能够与程序通信。 配对中的任一条指令都不会中断程序进行页面传送。 执行启动指令的处理器可以随时执行任何其他可用的指令。 虽然一对处理器可以执行一对指令，但该对可以由单独的处理器执行。 并且其他指令的执行可能在对的执行之间与页面传送重叠。

    Method and system for controlling references to system storage by overriding values
    7.
    发明授权
    Method and system for controlling references to system storage by overriding values 失效
    通过重写值来控制对系统存储引用的方法和系统

    公开(公告)号：US5615354A

    公开(公告)日：1997-03-25

    申请号：US471892

    申请日：1995-06-07

    申请人： Ronald F. Hill ,  Donald W. McCauley ,  Stephen J. Nadas ,  James R. Robinson

    发明人： Ronald F. Hill ,  Donald W. McCauley ,  Stephen J. Nadas ,  James R. Robinson

    IPC分类号： G06F9/312 ,  G06F9/318 ,  G06F9/355 ,  B06F9/06 ,  B06F13/10

    CPC分类号： G06F9/30043 ,  G06F9/3017 ,  G06F9/342

    摘要： A method and system for controlling references to system storage. Milli-code mode provides a flexible technique for overriding storage controls associated with referencing system storage of a data processing system. The storage controls to be overridden are not replaced and therefore, a restore of the previous contents of those controls is not necessary. This allows for an increase in system performance and an increase in the efficiency and flexibility of the system. In addition to the above, a system request instruction is provided, which enables flexibility in the manner in which system requests are executed. The flexibility of the system request instruction reduces the number of instructions needed to perform system requests.

    摘要翻译： 一种控制系统存储引用的方法和系统。 Milli代码模式提供了一种灵活的技术，用于覆盖与引用数据处理系统的系统存储相关联的存储控制。 要覆盖的存储控制不被替换，因此，这些控件的先前内容的恢复是不必要的。 这允许系统性能的提高和系统的效率和灵活性的提高。 除了上述之外，还提供了系统请求指令，其能够以执行系统请求的方式具有灵活性。 系统请求指令的灵活性减少了执行系统请求所需的指令数量。

    DATA CACHE PREFETCH THROTTLE
    9.
    发明申请
    DATA CACHE PREFETCH THROTTLE 有权

    公开(公告)号：US20130346703A1

    公开(公告)日：2013-12-26

    申请号：US13528302

    申请日：2012-06-20

    申请人： Donald W. McCauley ,  Stephen P. Thompson

    发明人： Donald W. McCauley ,  Stephen P. Thompson

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F2212/6024 ,  G06F2212/6026

    摘要： The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.

    摘要翻译： 本发明提供了一种用于节流缓存的预取请求的方法和装置。 该方法的一个实施例包括从响应于检测到第一地址的高速缓存未命中而选择用于将数据从存储器预取到高速缓存行的相对地址序列。 相对地址的序列相对于第一个地址确定。 该方法的该实施例还包括当至少一个先前预取流访问与该相对地址序列中的一个相关联的预取数据时，从由相对地址序列之一指示的存储器地址中发出数据的预取请求。