公开(公告)号：US11038051B2

公开(公告)日：2021-06-15

申请号：US16782823

申请日：2020-02-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro Mori

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate including a first epitaxial layer having a first surface and a second surface, a second epitaxial layer, a buried region formed across the first epitaxial layer and the second epitaxial layer, and a gate electrode. The second epitaxial layer includes a drain region, a source region, a body region, a drift region, a first region, and a second region. The first region is formed below at least the drain region. The second region has first and second ends in a channel length direction. The first end is located between the body region and the drain region in the channel length direction. The second region extends from the first end toward the second end such that the second end extends below at least the source region. An impurity concentration of the second region is greater than an impurity concentration of the first region.

公开(公告)号：US10388741B2

公开(公告)日：2019-08-20

申请号：US15411987

申请日：2017-01-21

Applicant: Renesas Electronics Corporation

Inventor： Takahiro Mori

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

Abstract: A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.

公开(公告)号：US20160284801A1

公开(公告)日：2016-09-29

申请号：US14399159

申请日：2013-11-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro Mori

IPC: H01L29/10 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: A semiconductor substrate has a recessed portion and a recessed portion in a main surface. An n+ source region and an n+ drain region sandwich the recessed portion and the recessed portion in the main surface. A p− epitaxial region and a p-type well region serving as a channel formation region are formed in the main surface between the n+ source region and the recessed portion. A gate electrode layer is formed on the channel region with a gate insulation film interposed therebetween, and extends onto an element isolation insulation film in the recessed portion. The recessed portion and the recessed portion are arranged to be adjacent to each other to sandwich a substrate protruding portion protruding toward the main surface side with respect to a bottom portion of each of the recessed portion and the recessed portion.

Abstract translation: 半导体基板在主表面上具有凹部和凹部。 n +源极区域和n +漏极区域夹着主表面中的凹部和凹部。 在n +源极区域和凹陷部分之间的主表面中形成用作沟道形成区域的p型外延区域和p型阱区域。 在沟道区域上形成栅电极层，其间插入有栅绝缘膜，并延伸到凹部中的元件隔离绝缘膜上。 凹部和凹部相互相邻配置，夹着相对于凹部和凹部各自的主面向主面侧突出的基板突出部。

公开(公告)号：US10483391B2

公开(公告)日：2019-11-19

申请号：US15845628

申请日：2017-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro Mori

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface, an insulating isolation film disposed at the first surface, and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The insulating isolation film has a first portion disposed inside the drift region in plan view, a second portion protruding from the first portion in a direction toward the source region, and a third portion protruding from the first portion in the direction toward the source region and sandwiching the drift region between the second portion and the third portion. The gate electrode faces a portion of the body region sandwiched between the source region and the drift region with being insulated from the portion. The gate electrode is disposed so as to extend over the second portion and the third portion.

公开(公告)号：US10340338B2

公开(公告)日：2019-07-02

申请号：US15810011

申请日：2017-11-11

Applicant: Renesas Electronics Corporation

Inventor： Takahiro Mori

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface, an insulating isolation structure having a first depth, and a gate electrode. The semiconductor substrate has source and drain regions, a reverse conductivity region having a second depth, a body region, and a drift region. The source region, the drift region, and the drain region are of a first conductivity type, and the body region and the reverse conductivity region are of a second conductivity type which is opposite to the first conductivity type. The insulating isolation structure is disposed between the drain region and the reverse conductivity region. The first depth is larger than the second depth.

公开(公告)号：US10217862B2

公开(公告)日：2019-02-26

申请号：US15837520

申请日：2017-12-11

Applicant: Renesas Electronics Corporation

Inventor： Takahiro Mori ,  Hiroki Fujii

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L29/10

Abstract: A semiconductor device including an isolation insulating film having a first thickness that is located between a drain region and a source region; a gate electrode formed over a region located between the isolation insulating film and the source region and that includes a part serving as a channel; an interlayer insulating film formed so as to cover the gate electrode; and a contact plug formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film, wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.

公开(公告)号：US09786594B2

公开(公告)日：2017-10-10

申请号：US14516806

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shigeo Tokumitsu ,  Takahiro Mori ,  Tetsuya Nitta

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L23/532

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

公开(公告)号：US09761714B2

公开(公告)日：2017-09-12

申请号：US14705511

申请日：2015-05-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro Mori

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7835 ,  H01L21/28052 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/408 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7816

Abstract: A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the gate electrode from a source region side toward a drain region side. The projection parts are arranged side by side along a second direction (direction orthogonal to a first direction along which the source region and the drain region are laid) in plan view. A plurality of openings is formed in the field oxide film. Each of the openings is located between projection parts adjacent to each other when seen from the first direction. The edge of the opening on the drain region side is located closer to the source region than the drain region. The edge of the opening on the source region side is located closer to the drain region than the side face of the gate electrode.

公开(公告)号：US09881868B2

公开(公告)日：2018-01-30

申请号：US14516806

申请日：2014-10-17

Applicant: Renesas Electronics Corporation

Inventor： Shigeo Tokumitsu ,  Takahiro Mori ,  Tetsuya Nitta

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/08 ,  H01L23/532

CPC classification number: H01L23/5228 ,  H01L23/53223 ,  H01L23/53266 ,  H01L27/0802 ,  H01L28/20 ,  H01L28/24 ,  H01L2224/05554

Abstract: A plurality of first wiring layers are arranged on a main surface of a substrate, a first insulating film is arranged on upper faces of the plurality of first wiring layers, a second insulating film is arranged on an upper face of the first insulating film, and a plurality of second wiring layers are arranged on the second insulating film. A metal resistive element layer is arranged just below at least one second wiring layer among the plurality of second wiring layers. A plurality of conductive layers extend from the plurality of second wiring layers respectively to the metal resistive element layer in a Z direction perpendicular to the main surface. The metal resistive element layer includes a metal wiring layer. At least one part of a side face of at least one conductive layer among the plurality of conductive layers is connected to the metal wiring layer.

公开(公告)号：US12293925B2

公开(公告)日：2025-05-06

申请号：US17894579

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki Murayama ,  Makoto Koshimizu ,  Takahiro Mori ,  Junjiro Sakai ,  Satoshi Iida

IPC: H01L21/4757 ,  H01L21/311 ,  H01L21/475 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532

Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.