公开(公告)号：US20160049470A1

公开(公告)日：2016-02-18

申请号：US14807757

申请日：2015-07-23

Applicant: Renesas Electronics Corporation

Inventor： Kiyoshi HAYASHI

IPC: H01L29/06 ,  H01L29/417 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/78

Abstract: A semiconductor device including a well resistance element of high accuracy and high withstand voltage and a method of manufacturing the semiconductor device are provided.The semiconductor device includes a semiconductor substrate, a well region, an input terminal, an output terminal, a separation insulating film, and an active region. The input terminal and the output terminal are electrically coupled to the well region. The separation insulating film is arranged to be in contact with the upper surface of the well region in an intermediate region between the input terminal and the output terminal. The active region is arranged to be in contact with the upper surface of the well region. The separation insulating film and the active region in the intermediate region have an elongated shape in plan view. In the intermediate region, a plurality of separation insulating films and a plurality of active regions are alternately and repeatedly arranged.

Abstract translation: 提供一种包括高精度和高耐压的阱电阻元件的半导体器件和制造半导体器件的方法。 半导体器件包括半导体衬底，阱区，输入端，输出端，隔离绝缘膜和有源区。 输入端子和输出端子电耦合到阱区域。 隔离绝缘膜被布置成在输入端子和输出端子之间的中间区域中与阱区域的上表面接触。 有源区域布置成与阱区域的上表面接触。 分离绝缘膜和中间区域中的有源区域在平面图中具有细长形状。 在中间区域中，多个隔离绝缘膜和多个有源区交替重复地布置。

公开(公告)号：US20170373146A1

公开(公告)日：2017-12-28

申请号：US15698219

申请日：2017-09-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyoshi HAYASHI

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/762 ,  H01L49/02 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device including a well resistance element of high accuracy and high withstand voltage and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a well region, an input terminal, an output terminal, a separation insulating film, and an active region. The input terminal and the output terminal are electrically coupled to the well region. The separation insulating film is arranged to be in contact with the upper surface of the well region in an intermediate region between the input terminal and the output terminal. The active region is arranged to be in contact with the upper surface of the well region. The separation insulating film and the active region in the intermediate region have an elongated shape in plan view. In the intermediate region, a plurality of separation insulating films and a plurality of active regions are alternately and repeatedly arranged.

公开(公告)号：US20160155825A1

公开(公告)日：2016-06-02

申请号：US15017459

申请日：2016-02-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiaki IWAMATSU ,  Takashi TERADA ,  Hirofumi SHINOHARA ,  Kozo ISHIKAWA ,  Ryuta TSUCHIYA ,  Kiyoshi HAYASHI

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/308 ,  H01L21/321

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.