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公开(公告)号：US10041841B2
公开(公告)日：2018-08-07
申请号：US15818357
申请日：2017-11-20
Applicant: Renesas Electronics Corporation
Inventor： Naoya Arisaka , Masataka Minami , Takahiro Miki
Abstract: A method of sensing a temperature of a semiconductor device, includes: measuring, by a time measuring circuit, time until a count value, which is obtained from a counter by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the counter; and obtaining, by the counter, a piece of digital information corresponding to the first voltage based on a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, based on the time measured by the time measuring circuit, the first voltage depending upon the temperature of the semiconductor device.
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公开(公告)号：US20160049188A1
公开(公告)日：2016-02-18
申请号：US14752514
申请日：2015-06-26
Applicant: Renesas Electronics Corporation
Inventor： Kenichi OSADA , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC: G11C11/417
CPC classification number: H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
Abstract: A P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one region is provided per group of thirty two memory cell rows or sixty four cell rows.
Abstract translation: 构成SRAM单元的逆变器的P型阱区域被细分成两部分，它们设置在N型阱区域NW1的相对侧上，并且形成为使得形成晶体管的扩散层具有 没有曲率，同时使得布局方向在平行于边界线和位线的方向上运行。 在阵列的中间位置处，以与字线平行的方式形成用于向基板供电的区域，以每组三十二个存储单元行或六十四个单元行提供一个区域。
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公开(公告)号：US10659026B2
公开(公告)日：2020-05-19
申请号：US16100370
申请日：2018-08-10
Applicant: Renesas Electronics Corporation
Inventor： Masataka Minami
Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.
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公开(公告)号：US20190123729A1
公开(公告)日：2019-04-25
申请号：US16100370
申请日：2018-08-10
Applicant: Renesas Electronics Corporation
Inventor： Masataka Minami
Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.
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公开(公告)号：US09891116B2
公开(公告)日：2018-02-13
申请号：US14459356
申请日：2014-08-14
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shigeki Obayashi , Hiroki Shimano , Masataka Minami , Hiroji Ozaki
IPC: G01K7/01
CPC classification number: G01K7/01
Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.
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Patent Agency Ranking
公开(公告)号：US09835499B2
公开(公告)日：2017-12-05
申请号：US14928856
申请日：2015-10-30
Applicant: Renesas Electronics Corporation
Inventor： Naoya Arisaka , Masataka Minami , Takahiro Miki
CPC classification number: G01K7/01 , G01K2217/00 , G01K2219/00 , H03K21/00 , H03K21/38
Abstract: The present invention provides a semiconductor device having a sensor capable of improving precision while suppressing increase in occupation area. A semiconductor device has: a first counter; and a second counter (time measuring circuit) measuring time until a count value, which is obtained by counting a first signal having a frequency corresponding to a first voltage, reaches a largest count value which can be counted by the first counter. The first counter obtains a piece of digital information corresponding to the first voltage on the basis of a count value obtained by counting a second signal having a frequency corresponding to a second voltage, which is different from the first voltage, on the basis of the time measured by the time measuring circuit.
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公开(公告)号：US11762034B2
公开(公告)日：2023-09-19
申请号：US17559091
申请日：2021-12-22
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tadashi Kameyama , Masanori Ikeda , Masataka Minami , Kenichi Shimada , Yukitoshi Tsuboi
IPC: G01R31/40
CPC classification number: G01R31/40
Abstract: The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.
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公开(公告)号：US10371582B2
公开(公告)日：2019-08-06
申请号：US15861819
申请日：2018-01-04
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shigeki Obayashi , Hiroki Shimano , Masataka Minami , Hiroji Ozaki
IPC: G01K7/01
Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.
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公开(公告)号：US20170179136A1
公开(公告)日：2017-06-22
申请号：US15448585
申请日：2017-03-02
Applicant: Renesas Electronics Corporation
Inventor： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC: H01L27/11 , H01L29/49 , H01L29/78 , G11C11/412
CPC classification number: H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
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公开(公告)号：US20160329091A1
公开(公告)日：2016-11-10
申请号：US15216327
申请日：2016-07-21
Applicant: Renesas Electronics Corporation
Inventor： Kenichi Osada , Masataka Minami , Shuji Ikeda , Koichiro Ishibashi
IPC: G11C11/412 , H01L27/11
CPC classification number: H01L27/1104 , G11C11/412 , G11C11/417 , H01L27/11 , H01L29/4916 , H01L29/783 , Y10S257/904
Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
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