公开(公告)号：US10229732B2

公开(公告)日：2019-03-12

申请号：US15876132

申请日：2018-01-20

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C5/06 ,  G11C11/419 ,  G11C5/14 ,  G11C11/417 ,  G11C11/412

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US20160071573A1

公开(公告)日：2016-03-10

申请号：US14940654

申请日：2015-11-13

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/417

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract translation: 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

公开(公告)号：US10446224B2

公开(公告)日：2019-10-15

申请号：US15887190

申请日：2018-02-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC: G11C11/417 ,  G11C5/14

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

公开(公告)号：US09922698B2

公开(公告)日：2018-03-20

申请号：US14484998

申请日：2014-09-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC: G11C11/417 ,  G11C5/14

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C5/148

Abstract: A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.

公开(公告)号：US20170206951A1

公开(公告)日：2017-07-20

申请号：US15478237

申请日：2017-04-03

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US20190172528A1

公开(公告)日：2019-06-06

申请号：US16271947

申请日：2019-02-11

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/419 ,  G11C11/412 ,  G11C5/14 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US20170179136A1

公开(公告)日：2017-06-22

申请号：US15448585

申请日：2017-03-02

Applicant: Renesas Electronics Corporation

Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

IPC: H01L27/11 ,  H01L29/49 ,  H01L29/78 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

公开(公告)号：US09658631B2

公开(公告)日：2017-05-23

申请号：US13862803

申请日：2013-04-15

Applicant: Renesas Electronics Corporation

Inventor： Ming Liu ,  Tatsuo Nakagawa ,  Kenichi Osada

IPC: G05F1/577 ,  G05F1/46 ,  H02M3/157 ,  H02M3/158 ,  H02M1/00

CPC classification number: H02M1/088 ,  G01R19/10 ,  G05F1/46 ,  G05F1/577 ,  H02M3/157 ,  H02M3/158 ,  H02M2001/0025 ,  H03M1/12 ,  Y10T307/406

Abstract: A conventional power supply device has a problem in miniaturization. A power supply device generates a prediction value of an error signal from first and second error signals, and controls an output voltage so that the prediction value lies between first and second threshold values. The first error signal is obtained by converting an error voltage based on the difference between the output voltage and a reference voltage at a first timing. The second error signal is obtained by converting an error voltage based on the difference between the output voltage and the reference voltage at a second timing.

公开(公告)号：US20160329091A1

公开(公告)日：2016-11-10

申请号：US15216327

申请日：2016-07-21

Applicant: Renesas Electronics Corporation

Inventor： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

IPC: G11C11/412 ,  H01L27/11

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

公开(公告)号：US09111636B2

公开(公告)日：2015-08-18

申请号：US14323064

申请日：2014-07-03

Applicant: Renesas Electronics Corporation

Inventor： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitoh ,  Akio Nishida ,  Masaru Nakamichi ,  Naoki Kitai

IPC: G11C11/40 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/412 ,  G11C11/40 ,  G11C11/413 ,  G11C11/418 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H03K19/0016

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.