公开(公告)号：US20190189737A1

公开(公告)日：2019-06-20

申请号：US16275469

申请日：2019-02-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Hideki NIWAYAMA ,  Kazuyuki UMEZU ,  Hiroki SOEDA ,  Atsushi TACHIGAMI ,  Takeshi IIJIMA

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/0649 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.

公开(公告)号：US20180061769A1

公开(公告)日：2018-03-01

申请号：US15640042

申请日：2017-06-30

Applicant: Renesas Electronics Corporation

Inventor： Toshikazu HANAWA ,  Kazuhide FUKAYA ,  Makoto KOSHIMIZU

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/53223 ,  H01L21/76802 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266

Abstract: An interlayer insulating film has via holes. A sidewall conductive layer is arranged along a sidewall surface of one via hole and contains one or more kinds selected from a group including tungsten, titanium, titanium nitride, tantalum and molybdenum. A second metal wiring layer is embedded in one via hole and contains aluminum. A plug layer is embedded in the other via hole and contains one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.

公开(公告)号：US20240047576A1

公开(公告)日：2024-02-08

申请号：US18490473

申请日：2023-10-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/045 ,  H01L29/66681

Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.

公开(公告)号：US20230065925A1

公开(公告)日：2023-03-02

申请号：US17867768

申请日：2022-07-19

Applicant: Renesas Electronics Corporation.

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor substrate has a surface and a convex portion projecting upward from the surface. An n-type drift region has a portion located in the convex portion. The n−-type drain region has a higher n-type impurity concentration than the n-type drift region, and is arranged in the convex portion and on the n-type drift region such that the n−-type drain region and a gate electrode sandwich the n-type drift region in plan view.

公开(公告)号：US20240145553A1

公开(公告)日：2024-05-02

申请号：US18051935

申请日：2022-11-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/7816

Abstract: LDMOS having an n-type source region and a drain region formed on an upper surface of a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate dielectric film, and a field plate electrode formed on the semiconductor substrate between the gate electrode and the drain region via a dielectric film having a larger film thickness than the gate dielectric film, is formed. Here, the field plate electrode has a larger work function than an n-type semiconductor region formed in the semiconductor substrate directly below the field plate electrode.

公开(公告)号：US20230231042A1

公开(公告)日：2023-07-20

申请号：US18055635

申请日：2022-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0657 ,  H01L29/861 ,  H01L29/66348

Abstract: A reliability of a semiconductor device is ensured, and performance of the device is improved. A semiconductor device including a region 1A and a region 2A includes an n-type semiconductor substrate TS having a front surface BS1, BS2 and a back surface SUB, a IGBT formed on a semiconductor substrate in a region 1A, and a diode formed on the semiconductor substrate SUB in a region 2A. And a thickness T1 of the semiconductor substrate SUB in the region 1A is smaller than a thickness of the semiconductor substrate T2 in the region 2A.

公开(公告)号：US20230057216A1

公开(公告)日：2023-02-23

申请号：US17876085

申请日：2022-07-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66

Abstract: A semiconductor device and a method of manufacturing the semiconductor device to achieve both of a high breakdown voltage and a low on resistance are provided. A semiconductor substrate includes a convex portion protruding upward from a surface of the semiconductor substrate. An n-type drift region is arranged on the semiconductor substrate so as to be positioned between a gate electrode and an n+-type drain region in plan view, and has an impurity concentration lower than an impurity concentration of the n+-type drain region. A p-type resurf region is arranged in the convex portion and forms a pn junction with the n-type drift region.

公开(公告)号：US20230069864A1

公开(公告)日：2023-03-09

申请号：US17894579

申请日：2022-08-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuki MURAYAMA ,  Makoto KOSHIMIZU ,  Takahiro MORI ,  Junjiro SAKAI ,  Satoshi IIDA

IPC: H01L21/4757 ,  H01L21/4763 ,  H01L21/475 ,  H01L23/31 ,  H01L23/532

Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

公开(公告)号：US20230022083A1

公开(公告)日：2023-01-26

申请号：US17380682

申请日：2021-07-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.

公开(公告)号：US20220393027A1

公开(公告)日：2022-12-08

申请号：US17722778

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: In semiconductor device, a field plate portion having a high concentration p-type semiconductor region, a low concentration p-type semiconductor region having a lower impurity concentration than the high concentration p-type semiconductor region and a high concentration n-type semiconductor region is provided. Then, the high concentration p-type semiconductor region is electrically connected to the source region while the high concentration n-type semiconductor region is electrically connected to the drain region.