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公开(公告)号:US20040178502A1
公开(公告)日:2004-09-16
申请号:US10698410
申请日:2003-11-03
Applicant: Renesas Technology Corp.
Inventor: Toshikazu Ishikawa , Takahiro Naito , Hiroshi Kuroda , Yoshinari Hayashi
IPC: H01L023/48
CPC classification number: H01L24/06 , H01L23/49811 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/06135 , H01L2224/06136 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01039 , H01L2924/0105 , H01L2924/01057 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/20759 , H01L2924/2076 , H01L2924/20757 , H01L2924/20758 , H01L2924/00012 , H01L2924/207
Abstract: A reduction in a size of a multichip module having a plurality of chips (higher-density mounting) and improvements in the reliability and functionality thereof are intended. By alternately repeating stacking in layers and processing of insulating films and conductive films, a microcomputer chip is face-down bonded to an upper portion of a wiring substrate having build-up substrate portions formed with wires with a surface of the microcomputer chip formed with a bump electrode facing downward. Memory chips are bonded onto an upper portion of the microcomputer chip with the respective surfaces thereof formed with bonding pads and the like facing upward. The bonding pads and the like are connected to bonding pads along edges of the wiring substrate with conductive wires. By thus disposing the microcomputer chip having multifunctionality and a larger number of terminals in a lower layer, the size reduction of a device and the like can be achieved.
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公开(公告)号:US20040140552A1
公开(公告)日:2004-07-22
申请号:US10737119
申请日:2003-12-17
Applicant: Renesas Technology Corp.
Inventor: Hiroshi Kuroda , Nobuhiro Kinoshita
IPC: H01L023/053
CPC classification number: H01L24/97 , H01L21/563 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48465 , H01L2224/49171 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/85201 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06562 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/01082 , H01L2924/00 , H01L2924/00012 , H01L2224/85 , H01L2224/83
Abstract: There is provided a small and high-performance System in Package (SiP) suitable for high-density mounting. A System in Package (SiP) has a stack structure such that two memory chips are stacked and mounted over the main surface of a wiring substrate, a microcomputer chip is stacked and mounted over the upper part thereof, and the chips are sealed by a mold resin. Each of the memory chips is constructed so as to transmit and receive data to/from the outside of the system via the microcomputer chip. The microcomputer chip is constructed of a multiport structure having various interfaces between it and the outside of the system in addition to an interface between it and the inside of the system. The number of terminals (pins) of the microcomputer chip is much larger than that of the memory chips.
Abstract translation: 提供了适用于高密度安装的小型和高性能系统级封装(SiP)。 包装系统(SiP)具有堆叠结构,使得两个存储芯片堆叠并安装在布线基板的主表面上,微计算机芯片堆叠并安装在其上部,并且芯片被模具密封 树脂。 每个存储器芯片被构造成经由微计算机芯片向/从系统的外部发送和接收数据。 除了其与系统内部的接口之外,微型计算机芯片由具有与系统外部各种接口的多端口结构构成。 微型计算机芯片的端子(引脚)数量远大于存储器芯片的数量。
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