公开(公告)号：US06720255B1

公开(公告)日：2004-04-13

申请号：US10318309

申请日：2002-12-12

申请人： Richard A. Faust ,  Noel M. Russell ,  Li Chen

发明人： Richard A. Faust ,  Noel M. Russell ,  Li Chen

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a dielectric layer (226) in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes (118) the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer (120) adjacent at least a portion of the dielectric layer.

摘要翻译： 一种制造形成在半导体晶片上的电子器件（200）的方法（100）。 该方法形成相对于晶片处于固定位置的介电层（226），其中介电层包括硅，碳和氧各自的原子浓度。 在形成步骤之后，该方法将电子器件暴露（118）到等离子体，使得电介质层的一部分中的碳的原子浓度增加，并且介电层的一部分中的氧的原子浓度降低。 在曝光步骤之后，该方法形成与电介质层的至少一部分相邻的阻挡层（120）。

公开(公告)号：US06723636B1

公开(公告)日：2004-04-20

申请号：US10447513

申请日：2003-05-28

申请人： Noel M. Russell ,  Kenneth Joseph Newton ,  Changming Jin

发明人： Noel M. Russell ,  Kenneth Joseph Newton ,  Changming Jin

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L21/7681 ,  H01L2221/1031

摘要： According to one embodiment of the invention, a method for forming multiple layers of a semiconductor device is provided. The method includes defining a via through a dielectric layer that overlies a first layer. The first layer comprises a conductive portion that at least partly underlies the via. The method also includes overfilling the via with a dielectric material to form a second layer that overlies the dielectric layer. The method also includes forming a trench that is connected to the via by etching through the second layer and the dielectric material in the via.

摘要翻译： 根据本发明的一个实施例，提供了一种用于形成半导体器件的多层的方法。 该方法包括通过覆盖在第一层上的电介质层限定通孔。 第一层包括至少部分地位于通孔下方的导电部分。 该方法还包括用电介质材料过填充通孔以形成覆盖在电介质层上的第二层。 该方法还包括通过蚀刻穿过第二层和通孔中的介电材料形成连接到通孔的沟槽。

公开(公告)号：US07037837B2

公开(公告)日：2006-05-02

申请号：US10903598

申请日：2004-07-29

申请人： Stephan Grunow ,  Satyavolu Srinivas Papa Rao ,  Noel M. Russell

发明人： Stephan Grunow ,  Satyavolu Srinivas Papa Rao ,  Noel M. Russell

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873

摘要： A method for fabricating a seed layer. A seed layer (126) is deposited over a barrier layer (124) using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.

公开(公告)号：US06900127B2

公开(公告)日：2005-05-31

申请号：US10649256

申请日：2003-08-27

申请人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Noel M. Russell

发明人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Noel M. Russell

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76846 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76862 ,  H01L21/76873

摘要： A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

摘要翻译： 沟槽（70）形成在电介质层（20）中。 使用物理气相沉积在沟槽中形成第一金属层（80）。 使用化学气相沉积在第一金属层（80）上的沟槽（70）中形成第二金属层（100）。 铜（110）用于通过将铜直接电镀到第二金属（100）上来填充沟槽（70）。

公开(公告)号：US07674707B2

公开(公告)日：2010-03-09

申请号：US11968093

申请日：2007-12-31

申请人： Noel M. Russell ,  Satyavolu Srinivas Papa Rao ,  Stephan Grunow

发明人： Noel M. Russell ,  Satyavolu Srinivas Papa Rao ,  Stephan Grunow

IPC分类号： H01L21/283

CPC分类号： C23C14/0641 ,  C23C14/0073 ,  H01L21/2855 ,  H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than

摘要翻译： 提供了设备和方法来在衬底上制造扩散阻挡层。 目前，使用需要多个点火步骤的物理气相沉积（PVD）工艺形成包括氮化物层和纯金属层的阻挡层，并且导致不小于2nm的氮化物层厚度。 本发明公开了生产小于1nm的氮化物层的装置和方法，同时允许在氮化物层上形成纯金属层而不再等离子体。 为了达到这个目的，在等离子体被点燃之前或在形成连续流动等离子体之前，氮气流被切断。 这确保了有限数量的氮原子与基底上的金属原子结合沉积，从而允许氮化物层的受控厚度。

公开(公告)号：US20090087956A1

公开(公告)日：2009-04-02

申请号：US11862668

申请日：2007-09-27

申请人： Satyavolu Srinivas Papa Rao ,  Mona M. Eissa ,  Christopher Lyle Borst ,  Noel M. Russell ,  Stanley Monroe Smith

发明人： Satyavolu Srinivas Papa Rao ,  Mona M. Eissa ,  Christopher Lyle Borst ,  Noel M. Russell ,  Stanley Monroe Smith

IPC分类号： H01L21/8238 ,  H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a high incidence of electrical shorts and reduced operating speed of the circuits. This problem is expected to worsen as feature sizes shrink in future technology nodes. This invention is an electrically non-functional contact, known as a dummy contact, that is utilized to attain a more uniform distribution of contacts across an IC, which allows contact fabrication processes to produce ICs with fewer defects, and a method for forming said dummy contacts in ICs.

摘要翻译： 最先进的集成电路（IC）包括各种电路，其具有在10至1000微米尺寸的区域中测量的各种接触密度。 触点的制造过程在同一个IC上具有高和低接触密度的困难，导致电短路的高发生率和电路的降低的操作速度。 随着未来技术节点的特征尺寸缩小，这个问题预计会恶化。 本发明是被称为虚拟接触件的电非功能性接触件，其用于实现跨越IC的更均匀的接触分布，这允许接触制造工艺制造具有较少缺陷的IC，以及用于形成所述虚拟器件的方法 IC中的联系人

公开(公告)号：US06291347B1

公开(公告)日：2001-09-18

申请号：US09671328

申请日：2000-09-26

申请人： Noel M. Russell ,  Anthony J. Konecni

发明人： Noel M. Russell ,  Anthony J. Konecni

IPC分类号： H01L2144

CPC分类号： C23C16/45597 ,  C23C16/18 ,  C23C16/4401 ,  C23C16/45591 ,  H01L21/28556

摘要： A system for constructing semiconductor devices is disclosed. The system comprises a wafer (102) having semiconductor devices (104), a bevel (108), an edge (110), a frontside (111), and a backside (112). The system also has a chamber (107), and a heater (106) coupled to the interior of the chamber (107) and operable to hold and heat the wafer (102). A showerhead (114) is also coupled to the interior of the chamber (107) and is operable to introduce a precursor gas (116) containing copper over the wafer (102). A shield (118) is coupled to the interior of the chamber (107) and is operable to partially shield the bevel (108), the edge (110), and the backside (112) of the wafer (102) from the precursor gas (116). There is an opening (122) in the chamber (107) through which a reactive backside gas (124) may be introduced under the wafer (102). A method for constructing semiconductor devices is disclosed. Step one calls for placing a wafer (102) on a heater (106) in a chamber (107). Step two requires heating the wafer with a heater (106). Step three provides for partially shielding the wafer (102) with a shield (118). In step four, the method provides for introducing a precursor gas (116) containing copper into the chamber (107) above the wafer (102). The last step calls for introducing a reactive backside gas (124) into the chamber (107) below the wafer (102) through an opening (122).

摘要翻译： 公开了一种用于构造半导体器件的系统。 该系统包括具有半导体器件（104），斜面（108），边缘（110），前侧（111）和背面（112）的晶片（102）。 该系统还具有室（107）和联接到室（107）的内部并且可操作以保持和加热晶片（102）的加热器（106）。 淋浴头（114）也联接到腔室（107）的内部，并且可操作以将含有铜的前体气体（116）引入晶片（102）上。 屏蔽件（118）联接到腔室（107）的内部并且可操作以将晶片（102）的斜面（108），边缘（110）和背面（112）部分地从前体气体 （116）。 在腔室（107）中有一个开口（122），反应性后侧气体（124）可以通过该开口引入晶片（102）下面。 公开了一种用于构造半导体器件的方法。 步骤一要求将晶片（102）放置在室（107）中的加热器（106）上。 第二步需要用加热器（106）加热晶片。 步骤三提供了用屏蔽件（118）部分地屏蔽晶片（102）。 在步骤四中，该方法提供了将含有铜的前体气体（116）引入晶片（102）上方的室（107）中。 最后一步要求通过开口（122）将反应后侧气体（124）引入晶片（102）下方的室（107）中。

公开(公告)号：US07256121B2

公开(公告)日：2007-08-14

申请号：US11002935

申请日：2004-12-02

申请人： Duofeng Yue ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Noel M. Russell ,  Montray Leavy

发明人： Duofeng Yue ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Noel M. Russell ,  Montray Leavy

IPC分类号： H01L21/4763

CPC分类号： H01L21/76814 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865

摘要： The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

摘要翻译： 本发明提供了一种在半导体衬底100上形成互连的方法。 该方法包括在开口130的内表面上形成开口230，沉积物在开口130的顶部附近形成折入轮廓。 势垒230的一部分被蚀刻，其移除阻挡物230的至少一部分以减少折返轮廓。 蚀刻还去除了开口130底部的阻挡层230的至少一部分。

公开(公告)号：US07148140B2

公开(公告)日：2006-12-12

申请号：US10901857

申请日：2004-07-28

申请人： Montray Leavy ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Noel M. Russell

发明人： Montray Leavy ,  Stephan Grunow ,  Satyavolu S. Papa Rao ,  Noel M. Russell

IPC分类号： H10L21/44

CPC分类号： H01L21/76877 ,  H01L21/76883

摘要： A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).

公开(公告)号：US06864108B1

公开(公告)日：2005-03-08

申请号：US10689218

申请日：2003-10-20

申请人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Noel M. Russell

发明人： Satyavolu S. Papa Rao ,  Stephan Grunow ,  Noel M. Russell

IPC分类号： G01K7/00 ,  G01K7/36 ,  H01L21/00

CPC分类号： G01K7/36 ,  G01K7/00 ,  H01L21/67248

摘要： A coil (50) is placed adjacent to a semiconductor wafer (10). An AC excitation current is used to create a changing electromagnetic field (60) is the wafer (10). The wafer is heated by a heat source (20) and the conductivity of the wafer (10) will change as a function of the wafer temperature. Induced eddy currents will cause the inductance of the coil (50) to change and the temperature of the wafer (10) can be determined by monitoring the inductance of the coil (50).

摘要翻译： 线圈（5​​0）被放置成与半导体晶片（10）相邻。 使用AC激励电流来产生晶片（10）的变化的电磁场（60）。 晶片被热源（20）加热，并且晶片（10）的导电率将随晶片温度的变化而变化。 引起的涡流将导致线圈（50）的电感改变，并且可以通过监测线圈（50）的电感来确定晶片（10）的温度。