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    Reductive alkylation of glycopeptide antibiotics
    2.
    发明授权
    Reductive alkylation of glycopeptide antibiotics 失效
    糖肽抗生素的还原烷基化

    公开(公告)号：US5952466A

    公开(公告)日：1999-09-14

    申请号：US968968

    申请日：1997-11-12

    申请人： Richard Alan Berglund ,  Nancy Anne Lockwood ,  Howard Eugene Magadanz ,  Hua Zheng

    发明人： Richard Alan Berglund ,  Nancy Anne Lockwood ,  Howard Eugene Magadanz ,  Hua Zheng

    IPC分类号： A61K38/00 ,  A61P31/00 ,  C07K9/00 ,  C07K5/12

    CPC分类号： C07K9/008 ,  A61K38/00

    摘要： This invention is concerned with improved processes for reductive alkylation of glycopeptide antibiotics. The improvement residing in providing a source of copper which results in the initial production of a copper complex of the glycopeptide antibiotic. Reductive alkylation of this complex favors regioselective alkylation and increased yields. Copper complexes of the glycopeptide antibiotic starting materials and of the alkylated products are also part of the invention.

    摘要翻译： 本发明涉及糖肽抗生素的还原烷基化改进方法。 提供的铜提供了一种铜的来源，导致糖肽抗生素的铜络合物的初始生产。 该复合物的还原烷基化有利于区域选择性烷基化和增加的产率。 糖肽抗生素原料和烷基化产物的铜络合物也是本发明的一部分。

    Dislplay panel, flat-panel display device and driving method thereof
    4.
    发明授权
    Dislplay panel, flat-panel display device and driving method thereof 有权
    显示面板，平板显示装置及其驱动方法

    公开(公告)号：US08896640B2

    公开(公告)日：2014-11-25

    申请号：US13578622

    申请日：2012-06-13

    申请人： Hua Zheng ,  Cheng-hung Chen

    发明人： Hua Zheng ,  Cheng-hung Chen

    IPC分类号： G09G5/10

    CPC分类号： G09G5/10 ,  G09G3/20 ,  G09G3/2092 ,  G09G2300/0408 ,  G09G2310/0281 ,  G09G2320/0223

    摘要： The display panel includes data driven chip and at least two scanning driven chips. The second scanning signal input terminal of each of the scanning driven chip is connected to a first scanning signal output terminal of the data driven chip by corresponding transmission circuits. At least one transmission circuit includes a serially connected resistor so that sum of impedance of the transmission circuits are equal, or the difference of the impedance of the transmission circuit is less than a predetermined value. In addition, a flat-panel display device with uniform brightness and a driving method thereof are also provided.

    摘要翻译： 显示面板包括数据驱动芯片和至少两个扫描驱动芯片。 每个扫描驱动芯片的第二扫描信号输入端通过相应的传输电路连接到数据驱动芯片的第一扫描信号输出端。 至少一个传输电路包括串联的电阻器，使得发送电路的阻抗之和相等，或者发送电路的阻抗差小于预定值。 此外，还提供了具有均匀亮度的平板显示装置及其驱动方法。

    Layer based scalable multimedia datastream compression
    6.
    发明申请
    Layer based scalable multimedia datastream compression 审中-公开
    基于层的可扩展多媒体数据流压缩

    公开(公告)号：US20080294446A1

    公开(公告)日：2008-11-27

    申请号：US11805245

    申请日：2007-05-22

    申请人： Linfeng Guo ,  Hua Zheng ,  Mark Sydorenko ,  Yang Li

    发明人： Linfeng Guo ,  Hua Zheng ,  Mark Sydorenko ,  Yang Li

    IPC分类号： G10L19/00

    CPC分类号： G10L19/167 ,  G10L19/0017 ,  G10L19/0204 ,  G10L19/24

    摘要： Source signals, such as audio and/or video data, are encoded into multiple, consecutive frequency bands. These bands are referred to as coding layers. Rather than performing complex bit-slice operations, a disclosed technique enables an agile and simplified response to transmission channel throughput variations. Specifically, if it becomes necessary to restrict the rate of data transmission to avoid receiver buffer underflow resulting from transmission channel degradation, layers from the transmitted signal are omitted, beginning with the highest frequency bands. Efficient and agile bit rate scalability during data streaming through wired or wireless networks and during local playback is thus enabled.

    摘要翻译： 诸如音频和/或视频数据的源信号被编码成多个连续的频带。 这些频带被称为编码层。 所公开的技术不是执行复杂的位片操作，而是能够对传输信道吞吐量变化进行敏捷和简化的响应。 具体地，如果需要限制数据传输速率以避免由于传输信道恶化导致的接收机缓冲器下溢，则从最高频带开始，从发送信号中省去层。 因此，通过有线或无线网络和本地播放期间的数据流传输期间，高效且敏捷的比特率可扩展性得以实现。

    Synchronous dynamic random access memory device
    9.
    发明授权
    Synchronous dynamic random access memory device 有权

    公开(公告)号：US06512711B1

    公开(公告)日：2003-01-28

    申请号：US09572820

    申请日：2000-05-16

    申请人： Jeffrey P. Wright ,  Hua Zheng

    发明人： Jeffrey P. Wright ,  Hua Zheng

    IPC分类号： G11C700

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109

    摘要： A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.